CPU Configuration
Intel SpeedStep Technology
Intel SpeedStep technology allows processors to switch between multiple frequencies
and voltage points for better power saving and heat dissipation.
Intel Turbo Boost Technology
Intel Turbo Boost Technology enables the processor to run above its base operating
frequency when the operating system requests the highest performance state.
Long Duration Power Limit
Configure Package Power Limit 1 in watts. When the limit is exceeded, the CPU
ratio will be lowered after a period of time. A lower limit can protect the CPU and
save power, while a higher limit may improve performance.
Because the UEFI software is constantly being updated, the following UEFI setup
screens and descriptions are for reference purpose only, and they may not exactly
match what you see on your screen.
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Long Duration Maintained
Configure the period of time until the CPU ratio is lowered when the Long
Duration Power Limit is exceeded.
Short Duration Power Limit
Configure Package Power Limit 2 in watts. When the limit is exceeded, the CPU
ratio will be lowered immediately. A lower limit can protect the CPU and save
power, while a higher limit may improve performance.
GT Frequency
Configure the frequency of the integrated GPU.
DRAM Configuration
DRAM Tweaker
Fine tune the DRAM settings by leaving marks in checkboxes. Click OK to confirm and
apply your new settings.
DRAM Timing Configuration
DRAM Reference Clock
Select Auto for optimized settings.
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted
and assign the appropriate frequency automatically.
Primary Timing
CAS# Latency (tCL)
The time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay and Row Precharge (tRCDtRP)
RAS# to CAS# Delay : The number of clock cycles required between the opening of a row
of memory and accessing columns within it.
Row Precharge: The number of clock cycles required between the issuing of the precharge
command and opening the next row.
RAS# Active Time (tRAS)
The number of clock cycles required between a bank active command and issuing the
precharge command.
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Command Rate (CR)
The delay between when a memory chip is selected and when the first active command can
be issued.
Secondary Timing
Write Recovery Time (tWR)
The amount of delay that must elapse after the completion of a valid write operation,
before an active bank can be precharged.
Refresh Cycle Time (tRFC)
The number of clocks from a Refresh command until the first Activate command to
the same rank.
RAS to RAS Delay (tRRD_L)
The number of clocks between two rows activated in different banks of the same
rank.
RAS to RAS Delay (tRRD_S)
The number of clocks between two rows activated in different banks of the same
rank.
Write to Read Delay (tWTR_L)
The number of clocks between the last valid write operation and the next read command to
the same internal bank.
Write to Read Delay (tWTR_S)
The number of clocks between the last valid write operation and the next read command to
the same internal bank.
Read to Precharge (tRTP)
The number of clocks that are inserted between a read command to a row precharge
command to the same rank.
Four Activate Window (tFAW)
The time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Configure CAS Write Latency.
Third Timing
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tREFI
Configure refresh cycles at an average periodic interval.
tCKE
Configure the period of time the DDR4 initiates a minimum of one refresh
command internally once it enters Self-Refresh mode.
tRDRD_sg
Configure between module read to read delay.
tRDRD_dg
Configure between module read to read delay.
tRDRD_dr
Configure between module read to read delay.
tRDRD_dd
Configure between module read to read delay.
tRDWR_sg
Configure between module read to write delay.
tRDWR_dg
Configure between module read to write delay.
tRDWR_dr
Configure between module read to write delay.
tRDWR_dd
Configure between module read to write delay.
tWRRD_sg
Configure between module write to read delay.
tWRRD_dg
Configure between module write to read delay.
tWRRD_dr
Configure between module write to read delay.
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tWRRD_dd
Configure between module write to read delay.
tWRWR_sg
Configure between module write to write delay.
tWRWR_dg
Configure between module write to write delay.
tWRWR_dr
Configure between module write to write delay.
tWRWR_dd
Configure between module write to write delay.
RTL Init Value
Configure round trip latency init value for round trip latency training.
IO-L Init Value
Configure IO latency init value for IO latency traning.
RTL (CH A)
Configure round trip latency for channel A.
RTL (CH B)
Configure round trip latency for channel B.
IO-L (CH A)
Configure IO latency for channel A.
IO-L (CH B)
Configure IO latency for channel B.
IO-L Offset (CH A)
Configure IO latency offset for channel A.
IO-L Offset (CH B)
Configure IO latency offset for channel B.
RFR Delay (CH A)
Configure RFR Delay for Channel A.
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RFR Delay (CH B)
Configure RFR Delay for Channel B.
Fourth Timing
twRPRE
Configure twRPRE.
Write_Early_ODT
Configure Write_Early_ODT.
tAONPD
Configure tAONPD.
tXP
Configure tXP.
tXPDLL
Configure tXPDLL.
tPRPDEN
Configure tPRPDEN.
tRDPDEN
Configure tRDPDEN.
twRPDEN
Configure twRPDEN.
OREF_RI
Configure OREF_RI.
tREFIx9
Configure tREFIx9.
txSDLL
Configure txSDLL.
txs_offset
Configure txs_offset.
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tZQOPER
Configure tZQOPER.
tMOD
Configure tMOD.
ZQCS_period
Configure ZQCS_period.
tZQCS
Configure tZQCS.
Advanced Setting
ODT WR (CH A)
Configure the memory on die termination resistors' WR for channel A.
ODT WR (CH B)
Configure the memory on die termination resistors' WR for channel B.
ODT PARK (CH A)
Configure the memory on die termination resistors' PARK for channel A.
ODT PARK (CH B)
Configure the memory on die termination resistors' PARK for channel B.
ODT NOM (CH A)
Use this to change ODT (CH A) Auto/Manual settings. The default is [Auto].
ODT NOM (CH B)
Use this to change ODT (CH B) Auto/Manual settings. The default is [Auto].
MRC Fast Boot
Enable Memory Fast Boot to skip DRAM memory training for booting faster.
Dll Bandwidth 0
Configure the Dll Bandwidth 0.
Dll Bandwidth 1
Configure the Dll Bandwidth 1.
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Dll Bandwidth 2
Configure the Dll Bandwidth 2.
Dll Bandwidth 3
Configure the Dll Bandwidth 3.
Margin Limit
Adjust Margin Limit to get better memory margin.
Voltage Configuration
CPU Vcore Voltage
Configure the voltage for the CPU Vcore.
GT Voltage
Configure the voltage for the integrated GPU
DRAM Voltage
Use this to configure DRAM Voltage. The default value is [Auto].
DRAM Activating Power Supply
Configure the voltage for the DRAM Activating Power Supply.
PCH +1.0 Voltage
Configure the chipset voltage (1.0V).
VCCSA Voltage
Configure the voltage for the VCCSA.
