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Someday we gonna see 8600 from you. Hopefully then 8800 too. But 8600 at least so i can sleep better :LOL: Once 8600 is done, 10400 or 12000MT/s G4, would be fun for you to run~ Because at this point why not. 10K strap is so so, but 10400MT/s is doable. Else 9600 MT/s it is ~ but that could be...

Powerprofile depends on you 320-320 is odd. But PL1/2 limiters generally can ruin memOC, because of low margins that get even lower when things start to downclock (irregularly) Depends how busy you are. I would not use HT-Off, ever It might work as bandaid, but too many bandaids = no peak...

Hey hey Do you mean the trouble on Romans Frame or the instability with the Mycro Copper Block at first ? Just watched Yes, he makes now basically everything right. Tolerances are fine. Awareness of Metalic above the trace (gap) is fine. His problem mostly come from wanting too much...

It was the reason you were never voltage stable to begin with Interesting about the speed drop. It has no need to do that unless you are actively hitting a power limiter. // Aware it will lower both IVRs due to hitting powerlimiters Ah thats resolvable. Yes very interesting that IVR VDDQ_IMC...

Ring + UCLK (MCLK rather i think), + X making QCLK Doesnt need to be the same value as Frontend P-Core Clk Both are connected PCLK & RingCLK But they are not the exact same frequency and are different IP Blocks. Downbin guarantees that dynamicness remains and CPU doesnt pump clock when it...

Yea no i mean, On such big ODT change a lot of options have to follow and correct. We depend on ASUS-HQ to have some sort of lookup table build in Because training can be good or bad, too much (on unstable state) training very much will be bad. 60 is the minimum that it can work and will work...

Ah its only written on the ICs sadly. Early we had RamMon by Passmark. but they updated it and now it doesnt display correctly the JEDEC binning of the ICs. Some bad ICs are JEDEC 4800 binned although follow A-Die 120ns RFC cap instead ~135-140ns M-Die. The ICs Branding next to the...

Those at worst can be 1-2 screws and need little loosening You can do that in runtime and test. But for now its ok, lets establish an actual baseline first. EDIT: I wish you wouldnt run HT-off, as there are better ways to handle scheduler assignment and will hide instability But that also can...

Its perfect :) Just explaining~ Haha Thank youu Now its behaving rather. mm mm, ddr5 is fun, isnt it :d Sorry i lost them, and this forum makes user-post lookup difficult What was that V/F curve of your sample. Seem to sweetspot SA here at 1.135 VID. Ok next change Im not sure if those are...

Thats great, well its not but its fun to test something then. Whenever you are not working. Also this is insane , haha. Be careful - at 300mV drop (due to under-/overshoot), PMIC and supply design might reach a limit. According to specifications it will. At this point of time, you may explore...

Yea it jumps too much still. Far too much Sadly i don't know why IVR drops soo much but only VDDQ_IMC and not VDD2_CPU. I am aware of how it behaves and it is a feature, with such big gap signaling an instability. But it doesn't resolve so far. So we need more work. I understand, but the...

Mmm its not too bad, but kind of not even close. (far too early for 8000) Also thank you~ Your IVR VDDQ_IMC does vanish tho. Its strange. Lets try something else Before that, can you re'run MC SP 5x and check how todays state is. I also notice you defined 18min as "done" You need it at very...

I need visual data :) Not words~~ Cant else help properly.

(y)

Any score anything ? please 1.15 SA Then same voltage down to 7800. Need to fix voltage/delta first before ever attempting 8000+

All "yes" Need to know if you can boot that

The "needs more, feed it more" part Was that purely by the SVID offset done ? Or you did also factor it in the loadline The loadline needs no touch , generally And this thing is bad Offset mode doesnt have to start at 0 Cache and so QCLK itself needs to downclock By it downclocking yet you...

Mm mm It can be due to powerlimiters or due to instability. Its a dynamic voltage at the end

Funny that slot B has lower bandwidth, slightly. This sounds like a ring issue tbh. Can you export me the Bios config ? Do you pass 2-3 rounds of CB15 Extreme (benchmate) ? Without it crashing ?

Here you have three things Basic signal, signal drive+filter, signal phase+speed You combine all 3 , to cover just one category change on signal alignment. They are different things, slopes are not the resolve to everything. How its feed matters , not the opposite. Not 100% confident on "E"...