Suchergebnisse

How do you undervolt the cores, just offseting the global SVID?

Yes, it's set it back to Windows Uefi.

Thank you! Did it like that, but getting a red secure boot error screen. Tried EFI shell too, same error. If the ODT's aren't exposed I won't continue to try that. :)

I know they are different, but somehow (indirectly) everything is connected to each other. For me the 1.53V / 1.47V VDD_MEM / VDDQ_MEM seems to be as a base. VDDQ_CPU is always a question and SA too. Maybe I should fix RTT's and set the Voltages to those. DQS could be the key, since it's based...

Yes, and since it's connected to VDD2 somehow, it can mess up the whole thing actually. Like a domino.

Yes, but that makes to change everything and start the research from the beginning. Who knows maybe that's the good way. Agree with the delta balance, for me 1.47V MEM_VDDQ is a must above 8400 and that affects the VDDQ_CPU too. SA is a dark horse for me. I can do 8400C36 with 1.12V SA, but I...

I don't know, this seems to be the most stable RON setting so far. But it could be because I have the foundation tuned for this. I was angry because I got random freeze in TM5 after 45-50 minutes, so I messed with the foundation a littl.e The freezes ware due to the TWTR L too tight, so channged...

This is really annoying. My max is 1.235V, 1.24 could already freeze in TM5.

Good job! The VDDQ_CPU is really nice and low! With P SP118 this CPU should be a beast too. :)

@Veii More playing with the 48/48 - 48/48 RON set. Raised VDDQ_MEM to 1.35V, reduced VDD2 to 1.512V. One more step forward. Bitrates are nice and constant. Strange, it didn't even lowered before the crash. Dunno, could be the ring too. It switches sometimes between 49-50X. If I give a little...

Yes, that's right but MEM_VDDQ never ever was nice under 1.47V for me. Maybe I have to choose the other way and reduce the mem delta with raising VDDQ. Lower RON was not good with the current voltage set. Maybe I need to revise the whole thing. @Veii Update Tried lower RON's, but it's no good...

Accc. to Hwinfo it doesn't hit it. The last point boost wants a lot of Vid.:) I need some time for that, but we are not in a hurry. :) I have a lot of work in the job. What makes me angry that it can't run 1 cycle now at all. When I change TX and retrain (I use the retrain button, that is like...

Nope, the first slot failed yesterday what setting, today it's passed. I retrained again and it's good now. Now the second slot under testing. Then I will set the Ctlvrefup as you suggested. Thank you and have a nice rest. 😊 Update Second slot passed too. VST is slower on this one. VT3 is...

We will see, but I believe we are close. First slot finished on 48/40 - 40/48 Starting to test the second slot.

It died in both slots, so I guess I need higher impedance. What I noticed that the dimms are using more power during Y if only only one slot is enabled.

I tried that first, Y stuck, posted a pic. Maybe a retrain would be enough, will try it again as the slot B will finish the current run. Haha, it finished very soon. 40/34 34/40 is no bueno.

Nope iot was 40/48 on both. Tried 40-34 34-40 on first slot

Used 40/48 on both. I will try that then. 40/34 34/40. They should be different due to the distance?

Yes, but only MC00 and MC01 RON could be set. The good thing I was able to pass both with the foundation we have. What should I do next?

Here you have it: bottom of the DRAM timing configuration menui. Controller 0 Channel 0/1 is SLOT A, Controller 1 Channel 0/1 is SLOT B.