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The boards trained timings are wrong quite a bit. I would imagine the tXP being too low has more of a negative impact than tCKE being too high, but who knows?

You can leave the sticks in and disable MC1 or MC0 in BIOS. I don't know if it is causing your issue, but tCKE should be 21 for 8267. I can't see what tXP is set to but it should be at 31. Your tCPDED is correct at 21.

24/4 is correct for H24M since WTRL should be RRDLx2 and RRDL runs at 12 most of the time on H24M. I'll try 0904. Probably still won't get 8400 stable but I won't know until I try!

...das Glueck, von mein Deutsch zu lesen!

I'm jelly that your RTLs train correctly. Mine only train correctly at 8400, no other frequencies train RTLs correctly. The funny thing is, 8400 won't stabilize on my CPU.

What about Channel B RTL R2-R7?

Thank you, Veii. I was able to get my correct tXSR.

Is tXSR dependent upon RFC or is it just frequency-dictated? I tried putting in my values in your RFC mini calculator but I don't know what I'm doing.

I've never had any success with it myself. Sugi0lover and a couple others have mentioned it. On another topic, I am trying to remember correct tCPDED calculation. Is it +1t to tCKE or equal to tCKE? I've always understood it to be 1t more than tCKE, but reading DDR5 spec says it is minimum 5ns...

Some people solve retrain inconsistency issues by setting ctlvrefup manually. I have personally not found this to be helpful to me, but I haven't been in this situation very often.

Sometimes it is not a spoon, but a ladle. :ROFLMAO:

Es tut sehr gut, deine Worte zu lesen. Apparently I am stalking you. Actually, someone on OCN linked that you were over here and I've been reading the thread. Another place to hopefully learn and mature my hobby. Hope you are well, my friend. Gruesse aus Californien.

Ich habe die GSkill 8400C40 1.4V. Die ICs sind nicht so gut wie 8200 1.35V. Sehr ähnlich, aber ~0.10mV schlimmer als 8200 1.35V bei der gleichen Frequenz/CL-Kombination.