Auch 1.25 und erhöhte CLDO VDDP sind ein nono. procODT von 40 auf 60 hochsteigend macht es zunehmend besser.
Wo fange ich bei den RTTs denn an? alle 34 und dann höher?
[Sammelthread] Ryzen DDR5 RAM OC Thread
- Ersteller Reous
- Erstellt am
Wo fange ich bei den RTTs denn an? alle 34 und dann höher?
Hast du ein Clear Cmos gemacht? Wie sieht es mit den Nitro Settings aus?
Bevor ich starte, würde ich evtl. Clear Cmos & oder das Bios neu flashen.
Danach würde ich mit niedrigen Spannungen starten, denn gerade gute Kits brauchen weniger & reagieren meist mit Fehlern auf zu viel.
Rtts würde ich mit off/off/6/5/6 nicht anfassen, das sieht gut aus. ProcODT & Dram DQDS beides auf 48 Ohm
CMOS Clear habe ich zwangsweise dazwischen machen müssen, da die Kiste manchmal im Bootscreen vom Bios schon crashed und ich es nichtmal schaffe defaults zu laden. Dann random Bluescreens beim booten. 7000Mhz geht, drüber dann eben die Symptome.
Ich flashe das Bios mal neu und stelle alles noch einmal mit 7600 from scratch ein.
Edit: Mal mit wenig Spannung angefangen, Timings alle AUTO, procODT und procDQDS 48Ohm.
Auch mit weniger VDDIO und co immernoch Aussetzer :/
Ich flashe das Bios mal neu und stelle alles noch einmal mit 7600 from scratch ein.
Edit: Mal mit wenig Spannung angefangen, Timings alle AUTO, procODT und procDQDS 48Ohm.
Auch mit weniger VDDIO und co immernoch Aussetzer :/
Anhänge
Zuletzt bearbeitet:
seppelchen
Foto-Master of 03/11
da bin ich schon bei dir...
Allerdings starte zuerst immer mit Auto um zu sehen ob es überhaupt läuft (stabil ist), dann erst gehts mit den Spannungen runter, die 1,32V bringen das Board nicht um. Gut, ich bin da eher der Laie und für mich ist das der leichtere Weg um den RAM auszuloten.
CLDO VDDP von 1,25V würde ich nicht probieren... Risiko ist hoch das die CPU einen Schaden davon trägt.
Deine Fehler führen auf einen IMC Problem zurück. Entweder dein Board mag die Riegel nicht oder etwas anderes funkt dazwischen. Probiere doch nochmal die Gskill aus ob es damit auf anhieb klappt.
seppelchen
Foto-Master of 03/11
Ok, für den 24/7 ich auch nicht... Allerdings hat jeder der EXPO lädt, die 1,3V (edit: VSoc) anliegen - daher sehe ich die Spannung (für den kurzzeitigen Betrieb) nicht so kritisch.
Zuletzt bearbeitet:
Du verwechselst es mit VSOC. CLDO VDDP ist für den PHY zuständig. Für 8000 reichen in der Regel 1,05V - 1,1V
Beitrag automatisch zusammengeführt:
Kannst du mir mal den Ram über Rammon auslesen und das Textdokument hier als Spoiler teilen?
Beitrag automatisch zusammengeführt:
Ich kann tatsächlich mit den Riegel bis 8800MTs ohne Probleme booten.
seppelchen
Foto-Master of 03/11
Ja klar meinte ich Vsoc, das hatte ich ja auf der letzten Seite geschrieben. Dann ist das wohl irgendwo in den falschen Hals gekommen.
Vielleicht VDDIO runter. Bei mir war 1.322 V der Weg zum Erfolg. Allerdings mit dem 7800x3d.
Dragonheart69
Enthusiast
Stimmt zuviel Spannung führt auch zu Instabilitäten.
Hier jetzt mit RAMMon
RAMMon v3.3 Build: 1000 built with SysInfo v3.0 Build: 2001
PassMark (R) Software
www.passmark.com
============================
Memory settings
============================
Transfer rate: 6200 MT/s
Memory timings: 28-36-32-48
Channel mode: 2
============================
Memory capacity / benchmarks
============================
L1 cache: 64 KB (315.1 GB/s)
L2 cache: 1024 KB (145.6 GB/s)
L3 cache: 65536 KB (99.0 GB/s)
Physical RAM: 47.6 GB (42422 MB/s)
Latency: 39.458 ns
============================
Memory SPD information
============================
Item | Slot #1 | Slot #2 | Slot #3 | Slot #4 |
---------------------------------------------------------------------------------------------------------------|----------------------------------------------------------------------------------------|----------------------------------------------------------------------------------------|-----------------|-----------------|-
Ram Type | DDR5 | DDR5 | Not Populated | Not Populated |
Maximum Clock Speed (MHz) | 4098 (XMP) | 4098 (XMP) | | |
Maximum Transfer Speed (MT/s) | DDR5-8196 | DDR5-8196 | | |
Maximum Bandwidth (MB/s) | PC5-32700 | PC5-32700 | | |
Memory Capacity (MB) | 24576 | 24576 | | |
DIMM Temperature | N/A | N/A | | |
Jedec Manufacture Name | Team Group Inc. | Team Group Inc. | | |
Search Amazon.com | Search! | Search! | | |
SPD Revision | 1.0 | 1.0 | | |
Registered | No | No | | |
ECC | No | No | | |
On-Die ECC | Yes | Yes | | |
DIMM Slot # | 1 | 2 | | |
Manufactured | Week 34 of Year 2024 | Week 34 of Year 2024 | | |
Module Part # | UD5-8200 | UD5-8200 | | |
Module Revision | 0x0 | 0x0 | | |
Module Serial # | 0104D92F (04ef0024340104d92f) | 0104D92C (04ef0024340104d92c) | | |
Module Manufacturing Location | 0 | 0 | | |
# of Row Addressing Bits | 17 | 17 | | |
# of Column Addressing Bits | 10 | 10 | | |
# of Banks | 32 | 32 | | |
# of Ranks | 1 | 1 | | |
Device Width in Bits | 8 | 8 | | |
Bus Width in Bits | 32 | 32 | | |
Module Voltage | 1.1V | 1.1V | | |
CAS Latencies Supported | 22 28 30 32 36 40 42 46 50 | 22 28 30 32 36 40 42 46 50 | | |
Timings @ Max Frequency (JEDEC) | 46-46-46-90 | 46-46-46-90 | | |
Maximum frequency (MHz) | 2800 | 2800 | | |
Maximum Transfer Speed (MT/s) | DDR5-5600 | DDR5-5600 | | |
Maximum Bandwidth (MB/s) | PC5-22400 | PC5-22400 | | |
Minimum Clock Cycle Time, tCK (ns) | 0.357 | 0.357 | | |
Minimum CAS Latency Time, tAA (ns) | 16.428 | 16.428 | | |
Minimum RAS to CAS Delay, tRCD (ns) | 16.428 | 16.428 | | |
Minimum Row Precharge Time, tRP (ns) | 16.428 | 16.428 | | |
Minimum Active to Precharge Time, tRAS (ns) | 32.000 | 32.000 | | |
Minimum Row Active to Row Active Delay, tRRD (ns) | 0.000 | 0.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Time, tRC (ns) | 48.428 | 48.428 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC (ns) | 410.000 | 410.000 | | |
| | | | |
DDR5 Specific SPD Attributes | | | | |
Maximum Clock Cycle Time, tCKmax (ns) | 1.010 | 1.010 | | |
Write Recovery time (ns) | 30.000 | 30.000 | | |
Minimum Auto-Refresh to Active/Auto Refresh Command Period, tRFC2 (ns) | 220.000 | 220.000 | | |
Minimum Auto-Refresh to Active/Auto Refresh Command Period, tRFC4 (ns) | 190.000 | 190.000 | | |
Minimum Refresh Recovery Delay Time, tRFC1 (ns) | 0.000 | 0.000 | | |
Minimum Refresh Recovery Delay Time, tRFC2 (ns) | 0.000 | 0.000 | | |
Minimum Refresh Recovery Delay Time, tRFCsb (ns) | 0.000 | 0.000 | | |
Module Type | UDIMM | UDIMM | | |
Module information SPD revision | 1.0 | 1.0 | | |
SPD present | Yes | Yes | | |
SPD device type | SPD5118 | SPD5118 | | |
SPD Manufacturer | Montage Technology Group (Bank: 7, ID: 0x32) | Montage Technology Group (Bank: 7, ID: 0x32) | | |
PMIC 0 present | Yes | Yes | | |
PMIC 0 device type | PMIC5100 | PMIC5100 | | |
PMIC 0 Manufacturer | Richtek Power (Bank: 11, ID: 0x8C) | Richtek Power (Bank: 11, ID: 0x8C) | | |
PMIC 1 present | No | No | | |
PMIC 1 device type | | | | |
PMIC 1 Manufacturer | | | | |
PMIC 2 present | No | No | | |
PMIC 2 device type | | | | |
PMIC 2 Manufacturer | | | | |
Thermal Sensor 0 present | No | No | | |
Thermal Sensor 1 present | No | No | | |
Thermal Sensor device type | | | | |
Thermal Sensor Manufacturer | | | | |
Module Height (mm) | 32 | 32 | | |
Module Thickness Front (mm) | 2 | 2 | | |
Module Thickness Back (mm) | 1 | 1 | | |
Module Reference Card | Raw Card A Rev. 0 | Raw Card A Rev. 0 | | |
# DRAM Rows | 1 | 1 | | |
Heat spreader installed | No | No | | |
Operating Temperature Range | XT (0 to + 95 °C) | XT (0 to + 95 °C) | | |
Rank Mix | Symmetrical | Symmetrical | | |
Number of Package Ranks per Channel | 1 | 1 | | |
Number of Channels per DIMM | 2 | 2 | | |
Primary bus width per Channel | 32 bits | 32 bits | | |
Bus width extension per Channel | 0 bits | 0 bits | | |
DRAM Manufacture ID | 173 | 173 | | |
DRAM Manufacture Bank | 1 | 1 | | |
DRAM Manufacture Name | SK Hynix | SK Hynix | | |
DRAM Stepping | 15.15 | 15.15 | | |
SDRAM Package Type | Monolithic SDRAM | Monolithic SDRAM | | |
SDRAM Density Per Die | 20Gb | 20Gb | | |
SDRAM Bank Groups | 8 | 8 | | |
SDRAM Banks Per Bank Group | 4 | 4 | | |
Second SDRAM Package Type | | | | |
Second SDRAM Density Per Die | | | | |
Second SDRAM Column Address Bits | | | | |
Second SDRAM Row Address Bits | | | | |
Second SDRAM Device Width | | | | |
Second SDRAM Bank Groups | | | | |
Second SDRAM Banks Per Bank Group | | | | |
First SDRAM RFM RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) | | |
First SDRAM RFM RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) | | |
First SDRAM RFM Required | no | no | | |
First SDRAM RFM RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 | | |
Second SDRAM RFM RAAMMT | | | | |
Second SDRAM RFM RAAIMT | | | | |
Second SDRAM RFM Required | | | | |
Second SDRAM RFM RAA Counter Decrement per REF command | | | | |
First SDRAM ARFM Level A RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) | | |
First SDRAM ARFM Level A RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) | | |
First SDRAM ARFM Level A supported | no | no | | |
First SDRAM ARFM Level A RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 | | |
Second SDRAM ARFM Level A RAAMMT | | | | |
Second SDRAM ARFM Level A RAAIMT | | | | |
Second SDRAM ARFM Level A supported | | | | |
Second SDRAM ARFM Level A RAA Counter Decrement per REF command | | | | |
First SDRAM ARFM Level B RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) | | |
First SDRAM ARFM Level B RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) | | |
First SDRAM ARFM Level B supported | no | no | | |
First SDRAM ARFM Level B RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 | | |
Second SDRAM ARFM Level B RAAMMT | | | | |
Second SDRAM ARFM Level B RAAIMT | | | | |
Second SDRAM ARFM Level B supported | | | | |
Second SDRAM ARFM Level B RAA Counter Decrement per REF command | | | | |
First SDRAM ARFM Level C RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) | | |
First SDRAM ARFM Level C RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) | | |
First SDRAM ARFM Level C supported | no | no | | |
First SDRAM ARFM Level C RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 | | |
Second SDRAM ARFM Level C RAAMMT | | | | |
Second SDRAM ARFM Level C RAAIMT | | | | |
Second SDRAM ARFM Level C supported | | | | |
Second SDRAM ARFM Level C RAA Counter Decrement per REF command | | | | |
sPPR Granularity | bank group | bank group | | |
sPPR Undo/Lock | supported | supported | | |
Burst length 32 | not supported | not supported | | |
MBIST/mPPR | not supported | not supported | | |
mPPR/hPPR Abort | not supported | not supported | | |
PASR | not supported | not supported | | |
DCA Types Supported | Device supports DCA for 4-phase internal clock(s) | Device supports DCA for 4-phase internal clock(s) | | |
x4 RMW/ECS Writeback Suppression | not supported | not supported | | |
x4 RMW/ECS Writeback Suppression MR selector | MR9 | MR9 | | |
Bounded Fault | not supported | not supported | | |
SDRAM Nominal Voltage, VDDQ | 1.1V | 1.1V | | |
SDRAM Nominal Voltage, VPP | 1.8V | 1.8V | | |
Cyclical Redundancy Code (CRC) for Base Configuration | 6fec | 6fec | | |
| | | | |
XMP Attributes | | | | |
XMP version | 3.0 | 3.0 | | |
PMIC Vendor ID | 8A8C | 8A8C | | |
Number of PMICs on DIMM | 1 | 1 | | |
PMIC capabilities | | | | |
PMIC has capabilities for OC functions | Yes | Yes | | |
Current PMIC OC is enabled | Yes | Yes | | |
PMIC voltage default step size | 5mV | 5mV | | |
OC global reset functions | No | No | | |
Validation and Certification Capabilities | | | | |
DIMM is self-certified by DIMM vendor | No | No | | |
PMIC Component is validated by Intel AVL level | No | No | | |
XMP revision | 1.2 | 1.2 | | |
XMP Profile 1 | | | | |
Profile name | TG-8200-38-49-84 | TG-8200-38-49-84 | | |
XMP Certified | No | No | | |
Recommended number of DIMMs per channel | 1 | 1 | | |
Module VPP voltage | 1.80V | 1.80V | | |
Module VDD voltage | 1.40V | 1.40V | | |
Module VDDQ voltage | 1.40V | 1.40V | | |
Memory Controller voltage | 1.10V | 1.10V | | |
Clock speed (MHz) | 4098 | 4098 | | |
Transfer Speed (MT/s) | DDR5-8196 | DDR5-8196 | | |
Bandwidth (MB/s) | PC5-32700 | PC5-32700 | | |
Minimum clock cycle time, tCK (ns) | 0.244 | 0.244 | | |
Supported CAS latencies | 38 | 38 | | |
Minimum CAS latency time, tAA (ns) | 9.272 | 9.272 | | |
Minimum RAS to CAS delay time, tRCD (ns) | 11.956 | 11.956 | | |
Minimum row precharge time, tRP (ns) | 11.956 | 11.956 | | |
Minimum active to precharge time, tRAS (ns) | 20.496 | 20.496 | | |
Supported timing at highest clock speed | 38-49-49-84 | 38-49-49-84 | | |
Minimum Active to Auto-Refresh Delay, tRC (ns) | 32.452 | 32.452 | | |
Minimum Write Recovery Time, tWR (ns) | 30.000 | 30.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC1 (ns) | 410.000 | 410.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC2 (ns) | 220.000 | 220.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFCsb (ns) | 190.000 | 190.000 | | |
Minimum Read to Read Command Delay Time, Same Bank Group, tCCD_L (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Write Command Delay Time, Same Bank Group, tCCD_L_WR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group, tCCD_L_WR2 (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Read Command Delay Time, Same Bank Group, tCCD_L_WTR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Read Command Delay Time, Different Bank Group, tCCD_S_WTR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Active to Active Command Delay Time, Same Bank Group, tRRD_L (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Read to Precharge Command Delay Time, tRTP (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Four Activate Window, tFAW (ns) | 0.000 | 0.000 | | |
Advanced Memory Overclocking Features | | | | |
Real-Time Memory Frequency Overclocking | Not supported | Not supported | | |
Intel Dynamic Memory Boost | Not supported | Not supported | | |
System CMD Rate Mode | 2N | 2N | | |
Vendor Personality Byte | 0x00 | 0x00 | | |
XMP Profile 2 | | | | |
Profile name | TG-6000-38-38-78 | TG-6000-38-38-78 | | |
XMP Certified | No | No | | |
Recommended number of DIMMs per channel | 1 | 1 | | |
Module VPP voltage | 1.80V | 1.80V | | |
Module VDD voltage | 1.25V | 1.25V | | |
Module VDDQ voltage | 1.25V | 1.25V | | |
Memory Controller voltage | 1.10V | 1.10V | | |
Clock speed (MHz) | 3000 | 3000 | | |
Transfer Speed (MT/s) | DDR5-6000 | DDR5-6000 | | |
Bandwidth (MB/s) | PC5-24000 | PC5-24000 | | |
Minimum clock cycle time, tCK (ns) | 0.333 | 0.333 | | |
Supported CAS latencies | 38 | 38 | | |
Minimum CAS latency time, tAA (ns) | 12.654 | 12.654 | | |
Minimum RAS to CAS delay time, tRCD (ns) | 12.654 | 12.654 | | |
Minimum row precharge time, tRP (ns) | 12.654 | 12.654 | | |
Minimum active to precharge time, tRAS (ns) | 25.974 | 25.974 | | |
Supported timing at highest clock speed | 38-38-38-78 | 38-38-38-78 | | |
Minimum Active to Auto-Refresh Delay, tRC (ns) | 38.628 | 38.628 | | |
Minimum Write Recovery Time, tWR (ns) | 30.000 | 30.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC1 (ns) | 410.000 | 410.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC2 (ns) | 220.000 | 220.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFCsb (ns) | 190.000 | 190.000 | | |
Minimum Read to Read Command Delay Time, Same Bank Group, tCCD_L (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Write Command Delay Time, Same Bank Group, tCCD_L_WR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group, tCCD_L_WR2 (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Read Command Delay Time, Same Bank Group, tCCD_L_WTR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Read Command Delay Time, Different Bank Group, tCCD_S_WTR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Active to Active Command Delay Time, Same Bank Group, tRRD_L (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Read to Precharge Command Delay Time, tRTP (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Four Activate Window, tFAW (ns) | 0.000 | 0.000 | | |
Advanced Memory Overclocking Features | | | | |
Real-Time Memory Frequency Overclocking | Not supported | Not supported | | |
Intel Dynamic Memory Boost | Not supported | Not supported | | |
System CMD Rate Mode | 2N | 2N | | |
Vendor Personality Byte | 0x00 | 0x00 | | |
XMP Profile 4 | | | | |
Profile name | Rewritable Profile 4 | Rewritable Profile 4 | | |
XMP Certified | No | No | | |
Recommended number of DIMMs per channel | 0 | 0 | | |
Module VPP voltage | 1.80V | 1.80V | | |
Module VDD voltage | 1.40V | 1.40V | | |
Module VDDQ voltage | 1.35V | 1.35V | | |
Memory Controller voltage | 1.35V | 1.35V | | |
Clock speed (MHz) | 3000 | 3000 | | |
Transfer Speed (MT/s) | DDR5-6000 | DDR5-6000 | | |
Bandwidth (MB/s) | PC5-24000 | PC5-24000 | | |
Minimum clock cycle time, tCK (ns) | 0.000 | 0.000 | | |
Supported CAS latencies | 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 ⼛䄕盉䅊盉䅊쫁䇏茓䈚슐䇯䏌䌰䌽 | 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 ⼛䄕盉䅊盉䅊쫁䇏茓䈚슐䇯䏌䌰䌽 | | |
Minimum CAS latency time, tAA (ns) | 9.324 | 9.324 | | |
Minimum RAS to CAS delay time, tRCD (ns) | 12.654 | 12.654 | | |
Minimum row precharge time, tRP (ns) | 12.654 | 12.654 | | |
Minimum active to precharge time, tRAS (ns) | 25.974 | 25.974 | | |
Supported timing at highest clock speed | -2147483648--2147483648--2147483648--2147483648 | -2147483648--2147483648--2147483648--2147483648 | | |
Minimum Active to Auto-Refresh Delay, tRC (ns) | 38.628 | 38.628 | | |
Minimum Write Recovery Time, tWR (ns) | 29.970 | 29.970 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC1 (ns) | 408.000 | 408.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC2 (ns) | 176.000 | 176.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFCsb (ns) | 189.000 | 189.000 | | |
Minimum Read to Read Command Delay Time, Same Bank Group, tCCD_L (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Write Command Delay Time, Same Bank Group, tCCD_L_WR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group, tCCD_L_WR2 (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Read Command Delay Time, Same Bank Group, tCCD_L_WTR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Read Command Delay Time, Different Bank Group, tCCD_S_WTR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Active to Active Command Delay Time, Same Bank Group, tRRD_L (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Read to Precharge Command Delay Time, tRTP (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Four Activate Window, tFAW (ns) | 0.000 | 0.000 | | |
Advanced Memory Overclocking Features | | | | |
Real-Time Memory Frequency Overclocking | Not supported | Not supported | | |
Intel Dynamic Memory Boost | Not supported | Not supported | | |
System CMD Rate Mode | 0N | 0N | | |
Vendor Personality Byte | 0x00 | 0x00 | | |
XMP Profile 5 | | | | |
Profile name | Rewritable Profile 5 | Rewritable Profile 5 | | |
XMP Certified | No | No | | |
Recommended number of DIMMs per channel | 0 | 0 | | |
Module VPP voltage | 1.80V | 1.80V | | |
Module VDD voltage | 1.40V | 1.40V | | |
Module VDDQ voltage | 1.40V | 1.40V | | |
Memory Controller voltage | 1.40V | 1.40V | | |
Clock speed (MHz) | 4000 | 4000 | | |
Transfer Speed (MT/s) | DDR5-8000 | DDR5-8000 | | |
Bandwidth (MB/s) | PC5-32000 | PC5-32000 | | |
Minimum clock cycle time, tCK (ns) | 0.000 | 0.000 | | |
Supported CAS latencies | 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 | 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 | | |
Minimum CAS latency time, tAA (ns) | 9.000 | 9.000 | | |
Minimum RAS to CAS delay time, tRCD (ns) | 12.250 | 12.250 | | |
Minimum row precharge time, tRP (ns) | 12.250 | 12.250 | | |
Minimum active to precharge time, tRAS (ns) | 21.000 | 21.000 | | |
Supported timing at highest clock speed | -2147483648--2147483648--2147483648--2147483648 | -2147483648--2147483648--2147483648--2147483648 | | |
Minimum Active to Auto-Refresh Delay, tRC (ns) | 32.750 | 32.750 | | |
Minimum Write Recovery Time, tWR (ns) | 22.500 | 22.500 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC1 (ns) | 410.000 | 410.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC2 (ns) | 220.000 | 220.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFCsb (ns) | 190.000 | 190.000 | | |
Minimum Read to Read Command Delay Time, Same Bank Group, tCCD_L (ns) | 10.240 (72 nCK) | 10.240 (72 nCK) | | |
Minimum Write to Write Command Delay Time, Same Bank Group, tCCD_L_WR (ns) | 36.978 (3 nCK) | 36.978 (0 nCK) | | |
Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group, tCCD_L_WR2 (ns) | 1.291 (6 nCK) | 1.288 (6 nCK) | | |
Minimum Write to Read Command Delay Time, Same Bank Group, tCCD_L_WTR (ns) | 0.087 (0 nCK) | 0.087 (0 nCK) | | |
Minimum Write to Read Command Delay Time, Different Bank Group, tCCD_S_WTR (ns) | 0.000 (1 nCK) | 0.000 (1 nCK) | | |
Minimum Active to Active Command Delay Time, Same Bank Group, tRRD_L (ns) | 0.000 (65 nCK) | 0.000 (65 nCK) | | |
Minimum Read to Precharge Command Delay Time, tRTP (ns) | 14.170 (57 nCK) | 14.170 (57 nCK) | | |
Minimum Four Activate Window, tFAW (ns) | 0.048 | 0.048 | | |
Advanced Memory Overclocking Features | | | | |
Real-Time Memory Frequency Overclocking | Not supported | Not supported | | |
Intel Dynamic Memory Boost | Supported | Supported | | |
System CMD Rate Mode | 1N | 2N | | |
Vendor Personality Byte | 0x22 | 0x22 | | |
PassMark (R) Software
www.passmark.com
============================
Memory settings
============================
Transfer rate: 6200 MT/s
Memory timings: 28-36-32-48
Channel mode: 2
============================
Memory capacity / benchmarks
============================
L1 cache: 64 KB (315.1 GB/s)
L2 cache: 1024 KB (145.6 GB/s)
L3 cache: 65536 KB (99.0 GB/s)
Physical RAM: 47.6 GB (42422 MB/s)
Latency: 39.458 ns
============================
Memory SPD information
============================
Item | Slot #1 | Slot #2 | Slot #3 | Slot #4 |
---------------------------------------------------------------------------------------------------------------|----------------------------------------------------------------------------------------|----------------------------------------------------------------------------------------|-----------------|-----------------|-
Ram Type | DDR5 | DDR5 | Not Populated | Not Populated |
Maximum Clock Speed (MHz) | 4098 (XMP) | 4098 (XMP) | | |
Maximum Transfer Speed (MT/s) | DDR5-8196 | DDR5-8196 | | |
Maximum Bandwidth (MB/s) | PC5-32700 | PC5-32700 | | |
Memory Capacity (MB) | 24576 | 24576 | | |
DIMM Temperature | N/A | N/A | | |
Jedec Manufacture Name | Team Group Inc. | Team Group Inc. | | |
Search Amazon.com | Search! | Search! | | |
SPD Revision | 1.0 | 1.0 | | |
Registered | No | No | | |
ECC | No | No | | |
On-Die ECC | Yes | Yes | | |
DIMM Slot # | 1 | 2 | | |
Manufactured | Week 34 of Year 2024 | Week 34 of Year 2024 | | |
Module Part # | UD5-8200 | UD5-8200 | | |
Module Revision | 0x0 | 0x0 | | |
Module Serial # | 0104D92F (04ef0024340104d92f) | 0104D92C (04ef0024340104d92c) | | |
Module Manufacturing Location | 0 | 0 | | |
# of Row Addressing Bits | 17 | 17 | | |
# of Column Addressing Bits | 10 | 10 | | |
# of Banks | 32 | 32 | | |
# of Ranks | 1 | 1 | | |
Device Width in Bits | 8 | 8 | | |
Bus Width in Bits | 32 | 32 | | |
Module Voltage | 1.1V | 1.1V | | |
CAS Latencies Supported | 22 28 30 32 36 40 42 46 50 | 22 28 30 32 36 40 42 46 50 | | |
Timings @ Max Frequency (JEDEC) | 46-46-46-90 | 46-46-46-90 | | |
Maximum frequency (MHz) | 2800 | 2800 | | |
Maximum Transfer Speed (MT/s) | DDR5-5600 | DDR5-5600 | | |
Maximum Bandwidth (MB/s) | PC5-22400 | PC5-22400 | | |
Minimum Clock Cycle Time, tCK (ns) | 0.357 | 0.357 | | |
Minimum CAS Latency Time, tAA (ns) | 16.428 | 16.428 | | |
Minimum RAS to CAS Delay, tRCD (ns) | 16.428 | 16.428 | | |
Minimum Row Precharge Time, tRP (ns) | 16.428 | 16.428 | | |
Minimum Active to Precharge Time, tRAS (ns) | 32.000 | 32.000 | | |
Minimum Row Active to Row Active Delay, tRRD (ns) | 0.000 | 0.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Time, tRC (ns) | 48.428 | 48.428 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC (ns) | 410.000 | 410.000 | | |
| | | | |
DDR5 Specific SPD Attributes | | | | |
Maximum Clock Cycle Time, tCKmax (ns) | 1.010 | 1.010 | | |
Write Recovery time (ns) | 30.000 | 30.000 | | |
Minimum Auto-Refresh to Active/Auto Refresh Command Period, tRFC2 (ns) | 220.000 | 220.000 | | |
Minimum Auto-Refresh to Active/Auto Refresh Command Period, tRFC4 (ns) | 190.000 | 190.000 | | |
Minimum Refresh Recovery Delay Time, tRFC1 (ns) | 0.000 | 0.000 | | |
Minimum Refresh Recovery Delay Time, tRFC2 (ns) | 0.000 | 0.000 | | |
Minimum Refresh Recovery Delay Time, tRFCsb (ns) | 0.000 | 0.000 | | |
Module Type | UDIMM | UDIMM | | |
Module information SPD revision | 1.0 | 1.0 | | |
SPD present | Yes | Yes | | |
SPD device type | SPD5118 | SPD5118 | | |
SPD Manufacturer | Montage Technology Group (Bank: 7, ID: 0x32) | Montage Technology Group (Bank: 7, ID: 0x32) | | |
PMIC 0 present | Yes | Yes | | |
PMIC 0 device type | PMIC5100 | PMIC5100 | | |
PMIC 0 Manufacturer | Richtek Power (Bank: 11, ID: 0x8C) | Richtek Power (Bank: 11, ID: 0x8C) | | |
PMIC 1 present | No | No | | |
PMIC 1 device type | | | | |
PMIC 1 Manufacturer | | | | |
PMIC 2 present | No | No | | |
PMIC 2 device type | | | | |
PMIC 2 Manufacturer | | | | |
Thermal Sensor 0 present | No | No | | |
Thermal Sensor 1 present | No | No | | |
Thermal Sensor device type | | | | |
Thermal Sensor Manufacturer | | | | |
Module Height (mm) | 32 | 32 | | |
Module Thickness Front (mm) | 2 | 2 | | |
Module Thickness Back (mm) | 1 | 1 | | |
Module Reference Card | Raw Card A Rev. 0 | Raw Card A Rev. 0 | | |
# DRAM Rows | 1 | 1 | | |
Heat spreader installed | No | No | | |
Operating Temperature Range | XT (0 to + 95 °C) | XT (0 to + 95 °C) | | |
Rank Mix | Symmetrical | Symmetrical | | |
Number of Package Ranks per Channel | 1 | 1 | | |
Number of Channels per DIMM | 2 | 2 | | |
Primary bus width per Channel | 32 bits | 32 bits | | |
Bus width extension per Channel | 0 bits | 0 bits | | |
DRAM Manufacture ID | 173 | 173 | | |
DRAM Manufacture Bank | 1 | 1 | | |
DRAM Manufacture Name | SK Hynix | SK Hynix | | |
DRAM Stepping | 15.15 | 15.15 | | |
SDRAM Package Type | Monolithic SDRAM | Monolithic SDRAM | | |
SDRAM Density Per Die | 20Gb | 20Gb | | |
SDRAM Bank Groups | 8 | 8 | | |
SDRAM Banks Per Bank Group | 4 | 4 | | |
Second SDRAM Package Type | | | | |
Second SDRAM Density Per Die | | | | |
Second SDRAM Column Address Bits | | | | |
Second SDRAM Row Address Bits | | | | |
Second SDRAM Device Width | | | | |
Second SDRAM Bank Groups | | | | |
Second SDRAM Banks Per Bank Group | | | | |
First SDRAM RFM RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) | | |
First SDRAM RFM RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) | | |
First SDRAM RFM Required | no | no | | |
First SDRAM RFM RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 | | |
Second SDRAM RFM RAAMMT | | | | |
Second SDRAM RFM RAAIMT | | | | |
Second SDRAM RFM Required | | | | |
Second SDRAM RFM RAA Counter Decrement per REF command | | | | |
First SDRAM ARFM Level A RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) | | |
First SDRAM ARFM Level A RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) | | |
First SDRAM ARFM Level A supported | no | no | | |
First SDRAM ARFM Level A RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 | | |
Second SDRAM ARFM Level A RAAMMT | | | | |
Second SDRAM ARFM Level A RAAIMT | | | | |
Second SDRAM ARFM Level A supported | | | | |
Second SDRAM ARFM Level A RAA Counter Decrement per REF command | | | | |
First SDRAM ARFM Level B RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) | | |
First SDRAM ARFM Level B RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) | | |
First SDRAM ARFM Level B supported | no | no | | |
First SDRAM ARFM Level B RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 | | |
Second SDRAM ARFM Level B RAAMMT | | | | |
Second SDRAM ARFM Level B RAAIMT | | | | |
Second SDRAM ARFM Level B supported | | | | |
Second SDRAM ARFM Level B RAA Counter Decrement per REF command | | | | |
First SDRAM ARFM Level C RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) | | |
First SDRAM ARFM Level C RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) | | |
First SDRAM ARFM Level C supported | no | no | | |
First SDRAM ARFM Level C RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 | | |
Second SDRAM ARFM Level C RAAMMT | | | | |
Second SDRAM ARFM Level C RAAIMT | | | | |
Second SDRAM ARFM Level C supported | | | | |
Second SDRAM ARFM Level C RAA Counter Decrement per REF command | | | | |
sPPR Granularity | bank group | bank group | | |
sPPR Undo/Lock | supported | supported | | |
Burst length 32 | not supported | not supported | | |
MBIST/mPPR | not supported | not supported | | |
mPPR/hPPR Abort | not supported | not supported | | |
PASR | not supported | not supported | | |
DCA Types Supported | Device supports DCA for 4-phase internal clock(s) | Device supports DCA for 4-phase internal clock(s) | | |
x4 RMW/ECS Writeback Suppression | not supported | not supported | | |
x4 RMW/ECS Writeback Suppression MR selector | MR9 | MR9 | | |
Bounded Fault | not supported | not supported | | |
SDRAM Nominal Voltage, VDDQ | 1.1V | 1.1V | | |
SDRAM Nominal Voltage, VPP | 1.8V | 1.8V | | |
Cyclical Redundancy Code (CRC) for Base Configuration | 6fec | 6fec | | |
| | | | |
XMP Attributes | | | | |
XMP version | 3.0 | 3.0 | | |
PMIC Vendor ID | 8A8C | 8A8C | | |
Number of PMICs on DIMM | 1 | 1 | | |
PMIC capabilities | | | | |
PMIC has capabilities for OC functions | Yes | Yes | | |
Current PMIC OC is enabled | Yes | Yes | | |
PMIC voltage default step size | 5mV | 5mV | | |
OC global reset functions | No | No | | |
Validation and Certification Capabilities | | | | |
DIMM is self-certified by DIMM vendor | No | No | | |
PMIC Component is validated by Intel AVL level | No | No | | |
XMP revision | 1.2 | 1.2 | | |
XMP Profile 1 | | | | |
Profile name | TG-8200-38-49-84 | TG-8200-38-49-84 | | |
XMP Certified | No | No | | |
Recommended number of DIMMs per channel | 1 | 1 | | |
Module VPP voltage | 1.80V | 1.80V | | |
Module VDD voltage | 1.40V | 1.40V | | |
Module VDDQ voltage | 1.40V | 1.40V | | |
Memory Controller voltage | 1.10V | 1.10V | | |
Clock speed (MHz) | 4098 | 4098 | | |
Transfer Speed (MT/s) | DDR5-8196 | DDR5-8196 | | |
Bandwidth (MB/s) | PC5-32700 | PC5-32700 | | |
Minimum clock cycle time, tCK (ns) | 0.244 | 0.244 | | |
Supported CAS latencies | 38 | 38 | | |
Minimum CAS latency time, tAA (ns) | 9.272 | 9.272 | | |
Minimum RAS to CAS delay time, tRCD (ns) | 11.956 | 11.956 | | |
Minimum row precharge time, tRP (ns) | 11.956 | 11.956 | | |
Minimum active to precharge time, tRAS (ns) | 20.496 | 20.496 | | |
Supported timing at highest clock speed | 38-49-49-84 | 38-49-49-84 | | |
Minimum Active to Auto-Refresh Delay, tRC (ns) | 32.452 | 32.452 | | |
Minimum Write Recovery Time, tWR (ns) | 30.000 | 30.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC1 (ns) | 410.000 | 410.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC2 (ns) | 220.000 | 220.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFCsb (ns) | 190.000 | 190.000 | | |
Minimum Read to Read Command Delay Time, Same Bank Group, tCCD_L (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Write Command Delay Time, Same Bank Group, tCCD_L_WR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group, tCCD_L_WR2 (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Read Command Delay Time, Same Bank Group, tCCD_L_WTR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Read Command Delay Time, Different Bank Group, tCCD_S_WTR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Active to Active Command Delay Time, Same Bank Group, tRRD_L (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Read to Precharge Command Delay Time, tRTP (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Four Activate Window, tFAW (ns) | 0.000 | 0.000 | | |
Advanced Memory Overclocking Features | | | | |
Real-Time Memory Frequency Overclocking | Not supported | Not supported | | |
Intel Dynamic Memory Boost | Not supported | Not supported | | |
System CMD Rate Mode | 2N | 2N | | |
Vendor Personality Byte | 0x00 | 0x00 | | |
XMP Profile 2 | | | | |
Profile name | TG-6000-38-38-78 | TG-6000-38-38-78 | | |
XMP Certified | No | No | | |
Recommended number of DIMMs per channel | 1 | 1 | | |
Module VPP voltage | 1.80V | 1.80V | | |
Module VDD voltage | 1.25V | 1.25V | | |
Module VDDQ voltage | 1.25V | 1.25V | | |
Memory Controller voltage | 1.10V | 1.10V | | |
Clock speed (MHz) | 3000 | 3000 | | |
Transfer Speed (MT/s) | DDR5-6000 | DDR5-6000 | | |
Bandwidth (MB/s) | PC5-24000 | PC5-24000 | | |
Minimum clock cycle time, tCK (ns) | 0.333 | 0.333 | | |
Supported CAS latencies | 38 | 38 | | |
Minimum CAS latency time, tAA (ns) | 12.654 | 12.654 | | |
Minimum RAS to CAS delay time, tRCD (ns) | 12.654 | 12.654 | | |
Minimum row precharge time, tRP (ns) | 12.654 | 12.654 | | |
Minimum active to precharge time, tRAS (ns) | 25.974 | 25.974 | | |
Supported timing at highest clock speed | 38-38-38-78 | 38-38-38-78 | | |
Minimum Active to Auto-Refresh Delay, tRC (ns) | 38.628 | 38.628 | | |
Minimum Write Recovery Time, tWR (ns) | 30.000 | 30.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC1 (ns) | 410.000 | 410.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC2 (ns) | 220.000 | 220.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFCsb (ns) | 190.000 | 190.000 | | |
Minimum Read to Read Command Delay Time, Same Bank Group, tCCD_L (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Write Command Delay Time, Same Bank Group, tCCD_L_WR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group, tCCD_L_WR2 (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Read Command Delay Time, Same Bank Group, tCCD_L_WTR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Read Command Delay Time, Different Bank Group, tCCD_S_WTR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Active to Active Command Delay Time, Same Bank Group, tRRD_L (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Read to Precharge Command Delay Time, tRTP (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Four Activate Window, tFAW (ns) | 0.000 | 0.000 | | |
Advanced Memory Overclocking Features | | | | |
Real-Time Memory Frequency Overclocking | Not supported | Not supported | | |
Intel Dynamic Memory Boost | Not supported | Not supported | | |
System CMD Rate Mode | 2N | 2N | | |
Vendor Personality Byte | 0x00 | 0x00 | | |
XMP Profile 4 | | | | |
Profile name | Rewritable Profile 4 | Rewritable Profile 4 | | |
XMP Certified | No | No | | |
Recommended number of DIMMs per channel | 0 | 0 | | |
Module VPP voltage | 1.80V | 1.80V | | |
Module VDD voltage | 1.40V | 1.40V | | |
Module VDDQ voltage | 1.35V | 1.35V | | |
Memory Controller voltage | 1.35V | 1.35V | | |
Clock speed (MHz) | 3000 | 3000 | | |
Transfer Speed (MT/s) | DDR5-6000 | DDR5-6000 | | |
Bandwidth (MB/s) | PC5-24000 | PC5-24000 | | |
Minimum clock cycle time, tCK (ns) | 0.000 | 0.000 | | |
Supported CAS latencies | 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 ⼛䄕盉䅊盉䅊쫁䇏茓䈚슐䇯䏌䌰䌽 | 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 ⼛䄕盉䅊盉䅊쫁䇏茓䈚슐䇯䏌䌰䌽 | | |
Minimum CAS latency time, tAA (ns) | 9.324 | 9.324 | | |
Minimum RAS to CAS delay time, tRCD (ns) | 12.654 | 12.654 | | |
Minimum row precharge time, tRP (ns) | 12.654 | 12.654 | | |
Minimum active to precharge time, tRAS (ns) | 25.974 | 25.974 | | |
Supported timing at highest clock speed | -2147483648--2147483648--2147483648--2147483648 | -2147483648--2147483648--2147483648--2147483648 | | |
Minimum Active to Auto-Refresh Delay, tRC (ns) | 38.628 | 38.628 | | |
Minimum Write Recovery Time, tWR (ns) | 29.970 | 29.970 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC1 (ns) | 408.000 | 408.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC2 (ns) | 176.000 | 176.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFCsb (ns) | 189.000 | 189.000 | | |
Minimum Read to Read Command Delay Time, Same Bank Group, tCCD_L (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Write Command Delay Time, Same Bank Group, tCCD_L_WR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group, tCCD_L_WR2 (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Read Command Delay Time, Same Bank Group, tCCD_L_WTR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Write to Read Command Delay Time, Different Bank Group, tCCD_S_WTR (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Active to Active Command Delay Time, Same Bank Group, tRRD_L (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Read to Precharge Command Delay Time, tRTP (ns) | 0.000 (0 nCK) | 0.000 (0 nCK) | | |
Minimum Four Activate Window, tFAW (ns) | 0.000 | 0.000 | | |
Advanced Memory Overclocking Features | | | | |
Real-Time Memory Frequency Overclocking | Not supported | Not supported | | |
Intel Dynamic Memory Boost | Not supported | Not supported | | |
System CMD Rate Mode | 0N | 0N | | |
Vendor Personality Byte | 0x00 | 0x00 | | |
XMP Profile 5 | | | | |
Profile name | Rewritable Profile 5 | Rewritable Profile 5 | | |
XMP Certified | No | No | | |
Recommended number of DIMMs per channel | 0 | 0 | | |
Module VPP voltage | 1.80V | 1.80V | | |
Module VDD voltage | 1.40V | 1.40V | | |
Module VDDQ voltage | 1.40V | 1.40V | | |
Memory Controller voltage | 1.40V | 1.40V | | |
Clock speed (MHz) | 4000 | 4000 | | |
Transfer Speed (MT/s) | DDR5-8000 | DDR5-8000 | | |
Bandwidth (MB/s) | PC5-32000 | PC5-32000 | | |
Minimum clock cycle time, tCK (ns) | 0.000 | 0.000 | | |
Supported CAS latencies | 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 | 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 | | |
Minimum CAS latency time, tAA (ns) | 9.000 | 9.000 | | |
Minimum RAS to CAS delay time, tRCD (ns) | 12.250 | 12.250 | | |
Minimum row precharge time, tRP (ns) | 12.250 | 12.250 | | |
Minimum active to precharge time, tRAS (ns) | 21.000 | 21.000 | | |
Supported timing at highest clock speed | -2147483648--2147483648--2147483648--2147483648 | -2147483648--2147483648--2147483648--2147483648 | | |
Minimum Active to Auto-Refresh Delay, tRC (ns) | 32.750 | 32.750 | | |
Minimum Write Recovery Time, tWR (ns) | 22.500 | 22.500 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC1 (ns) | 410.000 | 410.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC2 (ns) | 220.000 | 220.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFCsb (ns) | 190.000 | 190.000 | | |
Minimum Read to Read Command Delay Time, Same Bank Group, tCCD_L (ns) | 10.240 (72 nCK) | 10.240 (72 nCK) | | |
Minimum Write to Write Command Delay Time, Same Bank Group, tCCD_L_WR (ns) | 36.978 (3 nCK) | 36.978 (0 nCK) | | |
Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group, tCCD_L_WR2 (ns) | 1.291 (6 nCK) | 1.288 (6 nCK) | | |
Minimum Write to Read Command Delay Time, Same Bank Group, tCCD_L_WTR (ns) | 0.087 (0 nCK) | 0.087 (0 nCK) | | |
Minimum Write to Read Command Delay Time, Different Bank Group, tCCD_S_WTR (ns) | 0.000 (1 nCK) | 0.000 (1 nCK) | | |
Minimum Active to Active Command Delay Time, Same Bank Group, tRRD_L (ns) | 0.000 (65 nCK) | 0.000 (65 nCK) | | |
Minimum Read to Precharge Command Delay Time, tRTP (ns) | 14.170 (57 nCK) | 14.170 (57 nCK) | | |
Minimum Four Activate Window, tFAW (ns) | 0.048 | 0.048 | | |
Advanced Memory Overclocking Features | | | | |
Real-Time Memory Frequency Overclocking | Not supported | Not supported | | |
Intel Dynamic Memory Boost | Supported | Supported | | |
System CMD Rate Mode | 1N | 2N | | |
Vendor Personality Byte | 0x22 | 0x22 | | |
Zuletzt bearbeitet:
Für 6400 reichen mir auch 1.32 VDDIO, aber bei mehr drüber lande ich in 2F vom Mainboard. Also er braucht definitiv mehr vermute ich. Ist aber trotzdem alles etwas seltsam.
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