[Sammelthread] AMD K7 - Sockel A (462)

[bschicht86]

Normalerweise ist doch Barton erst ab 0340 gelockt. Beim Durchtesten bin ich über einen 2600+ gestolpert, der 0331 produziert wurde und beim verstellen des Mult im BIOS danach genauso hängt wie die jüngeren Brüder. Eine "Pilot-CPU"?

 

[digitalbath]

Ich habe auch einen 0336 Duron (1600), der gelockt ist.

 

[bschicht86]

Der Duron hat ja auch einen anderen Kern. Ich meine gelesen zu haben, dass jeder unterschiedliche Kern zu unterschiedlichen Wochen gelockt wurde, zuletzt eben der Barton. Weil ich hab nämlich auch Barton aus 0340 da, die noch offen sind. Der Unterschied von 9 Wochen wundert mich dann doch etwas.

 

[digitalbath]

oha, das wusste ich auch nicht. Danke für Info!

 

[Tzk]

Es wurden sogar verschiedene Steppings der gleichen Cpu unterschiedlich gelockt. Teilweise gibts welche aus den Wochen 40-45, die noch offen sind und andersrum welche, die ab Woche 30-35 schon locked sind. Ich hatte im Netz mal ne Liste gefunden wo jemand gesammelt hatte, abhängig von Stepping, Kern und Rating. Die ist ziemlich sicher hier verlinkt...

EDIT: https://forums.pcmatic.com/topic/42390-week-last-unlocked-barton-was-manufactured/

Einmal Spoiler ausklappen bitte

Spoiler: Superlock Stepping Liste

We're starting a data base of locked & unlocked chips:


locked: All week 43 (0343) to 46 Bartons and Thoroughbreds and most (but not all) post week 46 Bartons and Durons and:

AQZFA 0335 MPMW
AQZEA 0338

AQXCA 0340

AQXEA 0341 MPMW and VPMW

AQXFA 0339
AQXFA 0340 MPMW

AQYFA 0340 TPMW and UPAW and WPAW
AQYFA 0341 TPMW
AQYFA 0342

AQZEA 0341 TPMW and RPMW and RPDW

AQZFA 0339 UPMW and TPMW
AQZFA 0340 XPMW
AQZFA 0341 TPMW and SPMW and XPMW
AQZFA 0342 TPMW and UPMW (multiple confirmations of both locked and unlocked chips)
AQZFA 0341 VPMW

AQZFA 0347 XPMW

Thoroughbred JIXIB 0339
Thoroughbred AIXHB 0340 UPMW
Thoroughbred AIXHB 0341 SPMW

unlocked: Most made before week 35 and:

AQXFA 0340 MPMW and TPMW and UPMW and VPMW
AQYFA 0340 UPAW
AQZEA 0339 UPMW
AQZFA 0339 VMPW
AQZFA 0339 UMPW
AQZFA 0340 UPMW and SPMW and MPMW
AQZFA 0342 TPMW and UPMW (multiple confirmations of both locked and unlocked chips)


You see there is no stepping or week pattern, the only way to increase your chances is to try to get a pre week 35 Barton...

There is no visible physical difference between locked and unlocked chips because it appears changes were made inside the CPU core itself.

EDIT: quote:
Originally posted by ******
You can't tell the difference between locked and unlocked new chips with a naked eye or through codes.

The best we have is:

• All 2003 weeks 43 to 46 Bartons and Thoroughbreds are locked.

• Some weeks 35 to 43 are locked, some are not, and that includes Thoroughbreds, Thortons and Durons.

• There are rare cases of post 2003 week 46 unlocked Bartons and Durons.

 

[bschicht86]

Da werd ich wohl nochmal den Teil der locked vermuteten Bartons nochmal genauer anschauen.

 

[Tzk]

Wir können auch sehr gerne eine eigene Liste anlegen bzw. die aus dem Spoiler erweitern. Wenn du also testest, poste das ruhig hier.

 

[HerrAbisZ]

Sparksnl hat ja in seiner Sig eine Socket A spinning list - aber das wisst ihr ja sicher schon

 

[Tzk]

Ja, er selektiert nach Chipgüte. Wir meinen jetzt aber explizit ob sich der Multiplikator der Cpu verstellen lässt oder nicht. Er ist auch nicht der einzige mit so einer Liste...

 

[HerrAbisZ]

hat auch eine Spalte unlocked

 

[bschicht86]

Die ist aber bis auf einen Eintrag leer

 

[HerrAbisZ]

Du meinst jetzt aber die Locked von Tzk ?

 

[Tzk]

Jop. Da liegt Arbeit vor mir, deshalb ist meine Liste bis auf einen Eintrag (noch) leer Das sind fast alle Cpus die ich derzeit hier habe. Bei Sparks ist die Liste dagegen gut gefüllt.

 

[bschicht86]

Da liegt Arbeit vor mir

Bei mir erst. Ich hab schon einige Dutzend zusammen gesammelt, die zwischen 03/31 und 03/49 gefertigt wurden. (Nur Barton) Diese werd ich auf den Multi testen und es niederschreiben.

 

[Sparksnl]

Sparksnl hat ja in seiner Sig eine Socket A spinning list - aber das wisst ihr ja sicher schon

I never got around to it to add more cpu's. Feel free to add more here and extent the list.

 

[stunned_guy]

UPDATE der nF2 Liste

 

[Sparksnl]

I was testing an Athlon XP 3200+ today (AQXDA 0315 xxxx0015 or something like it). It boots 2500MHz at 1.725v or so. I thought, it might have potential. And then I found out that 2550MHz takes 1.95v and it does not run any MHz higher...

I still wonder if it could run way faster on cold. Any idea?

 

[I.nfraR.ed]

I'm working on the FSB control in the tweaker and it is somewhat working, but still can't get the real FSB that is displayed in the nf2 clockgen.
I've used/ported the driver from linux kernel, but it doesn't seem to work 100% correctly: https://github.com/torvalds/linux/blob/master/drivers/cpufreq/cpufreq-nforce2.c
Maybe I'm missing something, will keep trying.

 

[digitalbath]

FSB control in your tweaker would be nice. Keep on trying and good luck!

 

[The Sandman]

A save and load feature would also be nice. So far the tool is amazing. Lifting up the nF2 to new heights
thnx for your work!

 

[I.nfraR.ed]

The thing is this driver works with integer only, calculating fsb from pll multiplier and divider.
The PLL register is b0/d0/f0 reg A4 (dword).
When 200FSB is set, clockgen shows 200.49.
Value of the register is 005BF81F, where 5B varies, so I assume this somehow represents the value after the floating point.

0xF8 is the multiplier, 0x1F is the divider and the FSB is calculated by this equation

fsb = 25 * multiplier / divider

This is exactly 200.
What is left is the 0.49, 49 in hex is 0x31 and I don't see that value with RW opened and auto-refresh enabled.
0x5B is 91 in DEC

CPUZ jumps between 200.42 and 200.40. The value jumps between 0x5B and 0x59 (91 and 89 in DEC), so maybe divided by 200 or current FSB in int?

Let me know if you have some ideas how to calculate the remainder.

PS: Nah, it's always jumping between 0x5B and 0x59. Maybe it's calculated from the cpu frequency.

 

[The Sandman]

No clue bout coding stuff...

Does your LP B save settings like tref and different sips when using a modified bios that can choose different values, i.e. digitalbaths versions?
Mine simply doesn't.

Strangely enough the NF7 had the same problem when I did the L12 hardmod. Didn't save tref etc. After removing the mod it worked again

 

[I.nfraR.ed]

Never tried the LP B with digitalbath's modded bios, I don't really use that board often.

 

[The Sandman]

Too bad. It's quite invulnerable to SB bricking

 

[digitalbath]

@I.nfraR.ed
I want to help, but I am not sure if did understand your equasion.
for FSB 200 I also get on my machine F8 1F (1F=31DEC; F8=248DEC) -----> FSB=25*31/248 right? ----> FSB = 25*248/31 !

FSB 200,49 is F81F
FSB 210,86 is F41D
FSB 220,18 is F61C
FSB 230,19 is F81B
FSB 240,97 is FA1A
FSB 250,61 is FA19
FSB 260,00 is F918

edit:
corrected my equasion. now I understand.

 

[I.nfraR.ed]

Yes, that's correct. I just don't understand how clockgen calculates the next step when you click the right arrow and then how it gets the value after the floating point. Sometimes it is +0.83, sometimes +0.84, +0.85, + 0.86, +0.29...

 

[digitalbath]

Value of the register is 005BF81F, where 5B varies, so I assume this somehow represents the value after the floating point.

In my opinon this is right.
My setup is running FSB 240 at the moment. CPU-Z shows 240,5 (jumps sometimes to 240,6) and PCI regs shows 000EFA1A ----> FSB=(FA*25/1A)+0E/100=(250*25/26)+14/100=240,384+0,14=240,524 ?

The thing is, that the A4 values are strange. Sometimes the values after the floating point are changing permanently, sometimes not. I changed FSB with clockgen and restarted my system. After the restart, A4 PCI register showed old clockgen clocks not the BIOS clocks. Loading clockgen and read FSB and A4 register shows correct values.
I also can not change the A4 values manually.


edit:
maybe am wrong. This theory is not consistent. I will try more.

 

[The Sandman]

Remains of spread spectrum?
Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above. AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a maximum rate of 100 kHz.

https://en.wikichip.org/w/images/3/38/AMD_Athlon_XP_Processor_Model_10_Data_Sheet.pdf

Don't know...

 

[I.nfraR.ed]

edit:
maybe am wrong. This theory is not consistent. I will try more.

Yes, that's not it.
I think it is based on the current PLL (1MHz step) and the actual FSB is then calculated from that PLL value, current FID and CPU frequency.
Reading and settings FSB works, just need to add that calculation, so it can predict better what would be the actual FSB.

For example, if target is 208.00 (FSB derived from selected PLL value), then actual can be 207.xx or 208.xx. The selected divider is still the one that is used for 208.

 

[The-Unliving]

Nah nothing unshure someone deleting this !

Beitrag automatisch zusammengeführt: 08.05.2021

Muss ja nicht sein also beide Beiträge !

Beitrag automatisch zusammengeführt: 08.05.2021

Abwohl athlon -XP nur 2 Kerne ohne threads ? sockel überleg year 2002/3 ? Till 2004 ? aber bin da unsicher zu lange her ! x2600 nur zwo kerne ! 2,6 Ghz wissen null erinnern auch null..
erschwingliche 2 kern prozessorren ! irgendwas war da .. Ich Trinke zuviel aber um den dreh rum war das so ! vieleicht auch 2004