2.7.1.1 Ganging And Unganging
The following combinations of maximum bit widths (it is always possible to connect to a device using a supported,
narrower bit width), protocols, and frequencies are supported:
• One 16-bit link (ganged); either IO or coherent protocol; any supported link frequency. In ganged mode, the
link may or may not be left unconnected. In ganged mode, registers that control sublink 0 control the entire
link; registers that control sublink 1 are reserved.
• Two 8-bit links (unganged); the two sublinks may be configured for any combination of IO or coherent protocol,
AC- or DC-coupled mode (although AC-coupled IO links are not supported); if the two link frequencies
are the same, then they may be any supported frequency; if the two link frequencies are different, then
they are required to be one of the following ratios to each other: 8:1, 6:1, 4:1, 2:1; legal combinations are
{2.4, 0.4}, {4.8, 0.8}, {4.8, 2.4}, {4.8, 1.2}, {4.0, 2.0}, {3.2, 1.6}, {3.2, 0.8}, {3.2, 0.4}, {2.4, 1.2}, {1.6,
0.8}, {1.6, 0.4}, and {0.8, 0.4} GT/s). In unganged mode, neither, either, or both of the two 8-bit sublinks
may be left unconnected. In unganged mode, sublink 0 refers to the link associated with CLK[0], CTL[0],
and CAD[7:0]; sublink 1 refers to the link associated with CLK[1], CTL[1], and CAD[15:8].
2.7.1.2 Ganging Detection And Control
If unganging is not supported by the processor (F3xE8[UnGangEn]), then the links always cold boot to the
ganged state.
Otherwise, the ganged state of DC-coupled links at cold boot is based on the state of CTL[1]. If CTL[1]=0,
then the link powers up unganged. If CTL[1]=1, then the link powers up ganged. If CTL[1] is connected
between the processor and another devices (such as another processor) that supports the Gen3 link specification,
then the link cold boots to the unganged state.
If unganging is supported, AC-coupled links always cold boot to the unganged state.
If both sublinks of an unganged link connect the same two devices, then initialization software may be used to
place these sublinks into the ganged state (F0x[18C:170][Ganged]).
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2.8.4 Ganged or Unganged Mode Considerations
Typical systems built from multi-core products benefit from the additional parallelism generated by using the
two DCTs in unganged mode. Single core products or products that require additional ECC correction capabilities
(see 2.13.2 [DRAM Considerations for ECC] on page 118) should implement ganged mode.
When enabling two DCTs in unganged mode, BIOS should set F2x[
