Hi Leute!
Ich hab mich jetzt mal schlau gemacht, was die DDR-Speichertimings bedeuten. Ich hab folgendes gefunden:
PH Limit (Page Hit Limit)
Maximum number of consecutive page hits before choosing a non page hit request.
Idle Limit
AMD recommends 8 cycles.
Row Cycle Time (TRC) - less is better
Minimum time to activation of a bank.
RAS Precharge (TRP)
After reading a memory cell, the information usually gets lost, as the electric charge inside the cell is too small to conserve data integrity. To ensure consistency, data will always be written back into this memory cell. SDRAM requires 2 or 3 cycles precharge time for that.
RAS Active Time (TRAS) - less is better
Latency time before access to a non-addressed row within an open page (time from activate to precharge).
CAS Latency (CL) - less is better
After memory addressing, the system has to wait for the Column Address Strobe (CAS), which initiates the data transfer. Either two or 2.5 clock cycles, depending on the quality of memory (a half clock cycle is only possible with Double Data Rate memory). So far, there is hardly any PC2100 DDR SDRAM with CL2 available.
RAS-to-CAS Delay (TRCD) - less is better
The memory address information (which cell has to be read) is transferred in two steps: First the row address followed by the column address. Between that, the system takes a break of 2 or 3 cycles in order to separate those two values.
Though my testing memory from Micron officially only is a CL 2.5 module, it runs properly at CL2. I used the following settings:
PH Limit: 8
Idle Limit: 8
TRC: 5
TRP: 2
TRAS: 2
TCAS: 2
TRCD: 2
Meine Crucials laufen mit diesen schnellen Settings bis 144FSB.
DaKole
Ich hab mich jetzt mal schlau gemacht, was die DDR-Speichertimings bedeuten. Ich hab folgendes gefunden:
PH Limit (Page Hit Limit)
Maximum number of consecutive page hits before choosing a non page hit request.
Idle Limit
AMD recommends 8 cycles.
Row Cycle Time (TRC) - less is better
Minimum time to activation of a bank.
RAS Precharge (TRP)
After reading a memory cell, the information usually gets lost, as the electric charge inside the cell is too small to conserve data integrity. To ensure consistency, data will always be written back into this memory cell. SDRAM requires 2 or 3 cycles precharge time for that.
RAS Active Time (TRAS) - less is better
Latency time before access to a non-addressed row within an open page (time from activate to precharge).
CAS Latency (CL) - less is better
After memory addressing, the system has to wait for the Column Address Strobe (CAS), which initiates the data transfer. Either two or 2.5 clock cycles, depending on the quality of memory (a half clock cycle is only possible with Double Data Rate memory). So far, there is hardly any PC2100 DDR SDRAM with CL2 available.
RAS-to-CAS Delay (TRCD) - less is better
The memory address information (which cell has to be read) is transferred in two steps: First the row address followed by the column address. Between that, the system takes a break of 2 or 3 cycles in order to separate those two values.
Though my testing memory from Micron officially only is a CL 2.5 module, it runs properly at CL2. I used the following settings:
PH Limit: 8
Idle Limit: 8
TRC: 5
TRP: 2
TRAS: 2
TCAS: 2
TRCD: 2
Meine Crucials laufen mit diesen schnellen Settings bis 144FSB.
DaKole
