[Sammelthread] Intel DDR5 RAM OC Thread

[Braegnok]

Those values are purposefully wrong.
It's not the real values.
ASUS does not want to share settings so everyone could copy.

Those will change, if user sets something.

You want to start with RTT_WR only, but not now.
Target is 48-60ohm for 24gb kits.
All Hynix Target 80Ohm NOM.

Why only these?

NonK OC is a microcode thing.
Unless you focus specifically on the 2nd clockgen?


IA CEP Enable [Auto]
SA CEP Enable [Auto]
Both off
ICCMAX 400A, if 13th gen 320A

VDDQ training off

Ctl0 dqvrefup [Auto]
Ctl0 dqvrefdn [Auto]
178-96

Check again if 2 & 10
First check if 3 loops y-cruncher work at all.

RTT is usually @tibcsi0407 work
But lets see~

I did not set ICCMAX 400A, there are 3 shown in bios, all are in Auto,.. IVR Transmitter VDDQ ICCMAX, Unlimited ICCMAX, and IA SoC ICCMAX Reactive Protector,.. I would be guessing it's IVR Transmitter VDDQ ICEMAX?

Everything else set. Y Cruncher error @ start. Checking TM5 now.

 

[boesew1cht]

Kommt mir vertraut vor und liegt aktuell in meinem Budget. Ich habe halt paar Mal gesehen, wie man damit NonK OC betrieben hat. Stimmt es, wenn man nicht CPU OC betreibt, dass man eher DRR5 tunen kann, wegen Lower Ring Clock und oder Voltage? So habe ich Mal glatt 7600 getroffen, aber es war wohl pures Glück. Ring Down bin existiert eh nicht auf meinem Bord und Cache Ratio zu senken hat nicht wirklich geholfen.
Es reizt mich halt, endlich XMP Profile benutzen zu können, da es mir auf meinem Bord verwehrt wird. Zugegeben, von der Ram Materie habe ich keinen Plan und mit NonK und einem kastrierten Bord, mich durchzuboxen, habe ich echt satt.

Wegen dem Microcode; ja ist wohl so. Ältere Bios lassen sich nicht mehr einspielen und ich komme nicht mehr auf meine Spitze.
Genau, der externe Generator. Ich werde die Tage Mal eine andere CPU einstecken, bin mir schon fast sicher, dass alles mit dem Bord super funktioniert, wenn keine NonK drin ist. Ehrlich gesagt, bin ich richtig frustriert und kaufe mir "auch" deshalb jetzt ein neues Board. Ich könnte mir auch ein B760 Riptide holen (ich will sowieso ne neue Kiste bauen) und mein Bench Spaß auf Eis legen. Dabei über 400Euro sparen. Ich über lege noch

Welcher Microcode ist denn besonders "stabil" oder "gut" für ram oc? Bei mir kann ich im BIOS verschiedene Microcodes auswählen, weiß aber nicht ob das Sinn macht.

 

[Braegnok]

Cycle 1 is no errors, early into cycle 2 get error #6, then error #11.

Memory not showing in HwInfo64 after last bios adjustment, restart fixed. memory showing now. Going to save this profile, work on it tonight. Thanks.

 

[Nachzügler]

Welcher Microcode ist denn besonders "stabil" oder "gut" für ram oc? Bei mir kann ich im BIOS verschiedene Microcodes auswählen, weiß aber nicht ob das Sinn macht.

Sorry, da bin ich arg überfragt. Ich habe zwar ein paar Aorus Boards gehabt (eher sowas, wie B450 Pro Wifi), aber nicht neuere.

 

[Veii]

I did not set ICCMAX 400A, there are 3 shown in bios, all are in Auto,.. IVR Transmitter VDDQ ICCMAX, Unlimited ICCMAX, and IA SoC ICCMAX Reactive Protector,.. I would be guessing it's IVR Transmitter VDDQ ICEMAX?

Everything else set. Y Cruncher error @ start. Checking TM5 now.

Anhang anzeigen 966452 Anhang anzeigen 966453

mm mm unstable voltages.
And due to VDDQ Training off.
Thought you run it already

Try

I would be guessing it's IVR Transmitter VDDQ ICEMAX?

Yes.

Cycle 1 is no errors, early into cycle 2 get error #6, then error #11.

CPU is hard unstable, due to bad voltages. Likely bad VDDQ

VST & VT3 together
Else N63 and VT3 if you run the newer y-cruncher .

 

[Braegnok]

mm mm unstable voltages.
And due to VDDQ Training off.
Thought you run it already

Anhang anzeigen 966463
Try

Yes.

CPU is hard unstable, due to bad voltages. Likely bad VDDQ

VST & VT3 together
Else N63 and VT3 if you run the newer y-cruncher.

Going to take a break, go out and have lunch

I will reload 8400 profile tonight and set ICCMAX 400A, work on voltages. Should I enable VDDQ Training?

8400 profile is getting close, first time in 4-days passed cycle 1 with no errors,..

 

[Veii]

Should I enable VDDQ Training?

Never.

Beitrag automatisch zusammengeführt: 02.02.2024

Do the work and find the voltage for your Board & your dimms.
Don't take the easy route

 

[Vhypur]

1550mV
Not needed, but you can.

Ok cool thanks! i didn't think it was really needed but i did do a ton of benchmarks and game tests over the last couple days and had to figure out which v/f point was causing a freeze/error sometimes, took a bit but got that fixed now, while i'm here wanted to ask if you or anyone else knew exactly what these do or maybe an example of what they do

- enhanced TVB
- enhanced c-states -- think this just stops the cores from going below a certain mhz? and might need to be on for TVB to work but i don't think so?
- CPU power duty control
- CPU power phase control
- CPU Input Voltage Load-line Calibration -- this is the setting above LLC

 

[Braegnok]

mm mm unstable voltages.
And due to VDDQ Training off.
Thought you run it already

Anhang anzeigen 966463
Try

Yes.

CPU is hard unstable, due to bad voltages. Likely bad VDDQ

VST & VT3 together
Else N63 and VT3 if you run the newer y-cruncher.

Rolled back all timings to Auto, set Primarys to 40-52-52-134,.. testing.

RAM VDD 1.47V
RAM VDDQ 1.45V
SA 1.22V
TX 1.35V
IMC 1.36V

IVR Transmitter VDDQ ICCMAX is Max: 15(4A) I set @ 15.

 

[tibcsi0407]

Hello @Veii
A little progress.

TM5 is freezing after 4 cycles.
I raised tRAS and WtR a little. (24/8)
CPU VDDQ 1.35V
VDD2 1.518V
SA 1.23V
RAM VDD 1.56V
RAM VDDQ 1.47V
RX DFE off

Trying to adjust here and there to see what happens.
Maybe VDD is too much.

Update:
Changed to LLC5, IA_AC 0.08 (default V/F for the moment) and Eventual MC to 1.537V.

 

[Veii]

Rolled back all timings to Auto, set Primarys to 40-52-52-134 VDD 1.47v, VDDQ 1.45v, SA 1.22v, TX 1.35v, IMC 1.36v,.. testing.

IVR Transmitter VDDQ ICCMAX is Max: 15(4A) I set @ 15.

Anhang anzeigen 966553 Anhang anzeigen 966537

Mm mm then it wasnt that one only
There are two.
Its in the same place where you changed this one and can change vmax.

Hello @Veii
A little progress.

TM5 is freezing after 4 cycles.
I raised tRAS and WtR a little. (24/8)

You are cores/ring crashing.
RAS = RCD + RTP + X
Use +4
Its +X depends what type of data and how big of a chunk it needs to transfer from mem to cache

A read should be:
RAS lookup, CAS lookup, Bank Selector, Indefinite SenseAmp delay.
But many things happen at the same time
~ soo thinking in one operation book lecture is wrong and rulesets will be slow that way
Also RAS is a dynamic timing

You are not timings crashing
Messing up balance can also cause errors.

 

[tibcsi0407]

You are cores/ring crashing.
RAS = RCD + RTP + X
Use +4
Its +X depends what type of data and how big of a chunk it needs to transfer from mem to cache

Yeah, that's why changed on CPU.

I had an updated pic. Ran 20 minutes with LLC5 IA AC 0.08. Default V/F curve,
Set Eventual MC to 1.537V, so the trained one still 1.518V

Got error 11. Could be a refresh issue?
It freezed again. Strange.
I will reboot, adjust RAS and lower IA_AC, turn off TVB to see what happens. I can set it later with the V/F too.

Lowered TX to 1.33V, Eventual back to auto, VDD2 left on 1.518V
I can always run more than 10 minutes. I believe the loosened TWTR helped in this.
I have to revisit the RAM Voltages again, but I am closer than ever.

 

[Veii]

I had an updated pic. Ran 20 minutes with LLC5 IA AC 0.08. Default V/F curve,
Set Eventual MC to 1.537V, so the trained one still 1.518V

Old procedure is old procedur.
Its of the past

I just hope, it doesnt push you into misleading directions.

Not sure i understand the remain message.
But i hope you don't try to solve an old problem, based on an old foundation.
Because this indeed might just waste your time.

---

@elita sorry~

 

[tibcsi0407]

Old procedure is old procedur.
Its of the past

I just hope, it doesnt push you into misleading directions.

Not sure i understand the remain message.
But i hope you don't try to solve an old problem, based on an old foundation.
Because this indeed might just waste your time.

---

@elita sorry~

No, it's just experimenting with load lines and some old tricks. I will also try LLC3 and set the curve correctly with IA AC headroom.

 

[Veii]

No, it's just experimenting with load lines and some old tricks. I will also try LLC3 and set the curve correctly with IA AC headroom.

mm mm
elsehow it makes no sense
Cutting IA supply is not a good idea.

You have other issues to resolve
Dont mess with timings.

Its early to use tricks.
Hard work is required.
I gave suggestions already how to proceed
Slow and fun method.

Waiting for data.

 

[Veii]

- enhanced c-states -- think this just stops the cores from going below a certain mhz? and might need to be on for TVB to work but i don't think so?

- CPU power duty control
- CPU power phase control

🤭

 

[Vhypur]

Anhang anzeigen 966918

Anhang anzeigen 966921
🤭
Anhang anzeigen 966922

most obvious place to look and it didn't click in my head to check here lol thanks

 

[tibcsi0407]

mm mm
elsehow it makes no sense
Cutting IA supply is not a good idea.

You have other issues to resolve
Dont mess with timings.

Its early to use tricks.
Hard work is required.
I gave suggestions already how to proceed
Slow and fun method.

Waiting for data.

Good Morning @Veii

Changed LLC to Level 3, IA_AC is 0.65 now, adjusted V/F accordingly.
I like this LLC better so far, it's droopy, which is good for TVB boost Voltages.

So, set V/F and started Y.
Only thing I changed in Voltages is SA to 1.22V (from 1.23V)
It was able to run 30 minutes before error.
No tricks, only the main Voltages set, RTT, ODT on auto, CTL0 is 182/100, and the most important, no RX-DFE set, I left it on auto.
At iteration 5 VT3 I had to open the Chrome and do some business things, so the bitrate dropped there a little.
I don't think that Chrome caused the error. It's starting to be more promising, this is my record so far on this frequency.

I have no Idea what to change tbh at this point. Maybe I should play with the CPU VDDQ. The CPU VDDQ - RAM VDDQ delta I have is smaller (0.13V) than the delta I used to have. (0.15V)
Also, If I would have time to connect the chiller to the loop finally, maybe I could pass even with these settings.

Will run Usmus soon, just have to work a little on my projects.
I will also do the slot test you suggested, I think you will be right, one channel could need a little more Voltage.
Under TM5, the DIMM B always use more Power.

 

[Veii]

I have no Idea what to change tbh at this point.

Morniiing
But i told you already

Under TM5, the DIMM B always use more Power.

That's an ODT and RTT sideeffect.

I'd like you to first test which slot comes furthest
Do you pass it with one channel only (i would expect, else we need more work)

Then we have to fixate at a given PMIC voltage value (i think you do already, 15 [30mV] steps)
And with that track on TM5 (maybe pick HWMonitor here, cleaner pooling)
That there is no overshoot or undershoot between dimms.
No voltage jumping on load, as best as it can be.
This we can slowly track and work on. It will expose the actual mistakes
// Sometimes VDDQ is droopy on one channel, sometimes VDD is jumping given its too strong
// Sometimes 5v input is unstable, sometimes 1v & 1.8 show jumping which means it's missing voltage and corrects

Small things
But you either need to start pushing clock on Gear4
Soo CPU factor is as best as it can be removed & memory will require correct powering at 9600MT/s.
Or you need to inspect closer per channel behavior and maybe start with tuning RONs [Pull-Up/Down under ODT] ~ (of course disable its training point too)

RONs are board unique~
Even user/revision unique although Z690 & Z790 APEX liked the same RONs
Although with different RTTs and different ODTs ~ between us researchers.

Beitrag automatisch zusammengeführt: 04.02.2024

VPP_MEM topic needs to be isolated tracked.
IC Stability (internal transistors) for thermals, should mean that Wordline & Gate (basically VPP_MEM controlled)
Wouldn't need a change.

Its far too unlikely that JEDEC Committee made a design mistake (meaning it should always be ok at 1.8v)
~ but i remember i've also run 1.63v successfully instead of 1.8v on it, while other Boardpartners tend to push it regularly to 1.9v ~ even for XMP.
If it needs to be higher or lower due to strain and thermal factors (later shouldn't even matter for you)
You'd need to isolate it at least once, with TM5. Like test in 100mV steps what VPP_MEM works or does no change at all
// It's mostly helpful by hard #0 dropouts, but nevertheless is a factor.

EDIT:
I think per channel powering has much higher prio tho.

 

[tibcsi0407]

Morniiing
But i told you already

That's an ODT and RTT sideeffect.

I'd like you to first test which slot comes furthest
Do you pass it with one channel only (i would expect, else we need more work)

Then we have to fixate at a given PMIC voltage value (i think you do already, 15 [30mV] steps)
And with that track on TM5 (maybe pick HWMonitor here, cleaner pooling)
That there is no overshoot or undershoot between dimms.
No voltage jumping on load, as best as it can be.
This we can slowly track and work on. It will expose the actual mistakes
// Sometimes VDDQ is droopy on one channel, sometimes VDD is jumping given its too strong
// Sometimes 5v input is unstable, sometimes 1v & 1.8 show jumping which means it's missing voltage and corrects

Small things
But you either need to start pushing clock on Gear4
Soo CPU factor is as best as it can be removed & memory will require correct powering at 9600MT/s.
Or you need to inspect closer per channel behavior and maybe start with tuning RONs [Pull-Up/Down under ODT] ~ (of course disable its training point too)

RONs are board unique~
Even user/revision unique although Z690 & Z790 APEX liked the same RONs
Although with different RTTs and different ODTs ~ between us researchers.

Beitrag automatisch zusammengeführt: 04.02.2024

VPP_MEM topic needs to be isolated tracked.
IC Stability (internal transistors) for thermals, should mean that Wordline & Gate (basically VPP_MEM controlled)
Wouldn't need a change.
Anhang anzeigen 967002
Its far too unlikely that JEDEC Committee made a design mistake (meaning it should always be ok at 1.8v)
~ but i remember i've also run 1.63v successfully instead of 1.8v on it, while other Boardpartners tend to push it regularly to 1.9v ~ even for XMP.
If it needs to be higher or lower due to strain and thermal factors (later shouldn't even matter for you)
You'd need to isolate it at least once, with TM5. Like test in 100mV steps what VPP_MEM works or does no change at all
// It's mostly helpful by hard #0 dropouts, but nevertheless is a factor.

EDIT:
I think per channel powering has much higher prio tho.

Thank you. I will do the per channel test tomorrow.
Today is just crazy.
The voltage jumps could be really the part of my issue.
But TM5 is still freezing around 45 minutes. Something should be changed on my settings, it's hard to find the issue.

Update

How can I turn off the dimm slot completely? Itried to disable channels in BIOS, but I can only disable half of the dimms.
Edit
Solved🙃

 

[Veii]

Update

How can I turn off the dimm slot completely? Itried to disable channels in BIOS, but I can only disable half of the dimms.
Edit
Solved🙃

2 MC links per channel
Board trace testing = turning one MC link off
Memory slot & CPU testing = tuning one channel off.

But TM5 is still freezing around 45 minutes. Something should be changed on my settings, it's hard to find the issue.

Idle freeze maybe ?
mmmmm

Beitrag automatisch zusammengeführt: 04.02.2024

Today is just crazy.

Oh , RL ??

Beitrag automatisch zusammengeführt: 04.02.2024

The voltage jumps could be really the part of my issue.

Nearly everyone has this.
To what i can track.
But it can be better~~

SPD Hub is very intelligent
Its not easy.

 

[tibcsi0407]

Idle freeze maybe ?
mmmmm

Not in idle, about 45-50 minutes of TM5 run.

Oh , RL ??

My daughter does the entertain for us. 😂



I will run 20 cycles for each speed and channel. Will try to go until 9000 awe will see.
And Y of course.
I believe 8800 should work per slot. I can boot and even bench on 8800. Didn't try higher yet.

 

[Veii]

Not in idle, about 45-50 minutes of TM5 run.

Yes, but freeze on pause mid test maybe
Else it will spill an error

I am not sure if new TM5 is 100% trustable
But i think its pause on idle load, else TM5 would catch it.
EDIT:
Can be ring, can be just V/F - likely V/F is main reason.

My daughter does the entertain for us. 😂

🤭

I will run 20 cycles for each speed and channel. Will try to go until 9000 awe will see.

Gear 4 bellow 9600 will not boot
Gear 2 above 8800 is very difficult
For many 8600 is impossible.

 

[tibcsi0407]

Gear 4 bellow 9600 will not boot
Gear 2 above 8800 is very difficult
For many 8600 is impossible

After the 30 minutes Y today I am starting to belive that I can do the 8600.
Everything else is a bonus for me. 🙃

 

[Veii]

After the 30 minutes Y today I am starting to belive that I can do the 8600.
Everything else is a bonus for me. 🙃

G4 is a different path to take
we need 10000MT/s and higher, for it to make sense
Bellow 9600MT/s, it can not boot.

But your goal is fixing noise.
Not lowering voltage, not lowering timing
Fixing bad powering, to utilize 24gb better.

---

Your goal is achieving stability on high voltage, not finding stability with lower voltage
and your current goal (i recommend) is to find small issues and remove them.
Not take easy route and accept defeat 😌

IMC is not so weak, like many say.
Its amount of work, that is lacking~

 

[snakeeyes]

Gear 4 bellow 9600 will not boot

ez on apex. Did 9200- 9600 ez everytime.

 

[Veii]

ez on apex. Did 9200- 9600 ez everytime.

Maybe something changed from before.
Bellow 9600MT/s it can not boot.
Maybe i got wrong information, but i believe source.

Just we are past "booting" attempts.

 

[tibcsi0407]

G4 is a different path to take
we need 10000MT/s and higher, for it to make sense
Bellow 9600MT/s, it can not boot.

But your goal is fixing noise.
Not lowering voltage, not lowering timing
Fixing bad powering, to utilize 24gb better.

---

Your goal is achieving stability on high voltage, not finding stability with lower voltage
and your current goal (i recommend) is to find small issues and remove them.
Not take easy route and accept defeat 😌

IMC is not so weak, like many say.
Its amount of work, that is lacking~

Yes, since I can cool it, high Voltage is not an issue.
Do you have example screenshot for Gear 4 timings and Voltages?

 

[Veii]

Do you have example screenshot for Gear 4 timings and Voltages?

I gave already~~
Not in picture format.

Its "doable" with one channel
and kind of requirement at first

both channels its difficult.
often its not even one channel , but one MC-Link only

Beitrag automatisch zusammengeführt: 04.02.2024

soo given difficulty
It will help you isolate issues better
And remove strain from cpu side.

 

[tibcsi0407]

I gave already~~
Not in picture format.

Its "doable" with one channel
and kind of requirement at first

both channels its difficult.
often its not even one channel , but one MC-Link only

Beitrag automatisch zusammengeführt: 04.02.2024

soo given difficulty
It will help you isolate issues better
And remove strain from cpu side.

I will check it. Dimm 1 8600 is done, Dimm 2 8600 is running now. That should be weakest slot