Intel i865PE Memory register
Zum Intel 865PE gibt es von Intel ein Datenblatt mit darin enthaltenen Informationen wo die Speicher Einstellungen in den Registern gespeichert wird. Leider hat Intel nicht alle Informationen in das Datenblatt eingetragen. Ich denke mal, das hat einen Grund. Ich habe jedenfalls mit Hilfe von memset einige Register herausgefunden und konnte so die Intel Informationen ergänzen.
Achtung! Das wird ein längerer Post!
Die Haupttimings vom 865PE liegen in dem sogenanten „Memory-Mapped I/O Register Space“. Das bedeutet diese Werte liegen nicht in den normal adressierten PCI register. Die Adresse zu diesem Memory I/O Space liegt im PCI register
b0d6f0 register
10h. Mit dem RWEverything kann ich den PCI Register Bereich
b0d6f0 erst sehen wenn ich Memset starte und es im Hintergrund liegt. Warum das so ist, weiß ich nicht. Mit einem Doppelklick auf den 32bit register
10h öffnet RWE automatisch den korrekten Bereich vom Memory I/O Space. In meinem Fall ist das “
FECF 0000“. Dann kann ich die Speichereinstellungen ändern. Es gibt darin zwei für uns wichtige 32bit register. Register 60h (60h bis 63h) ist für
DRAM Timing und Register 68h (68h bis 6Bh) ist für
DRAM Controller Mode zuständig.
Hier die Auflistung der Register:
DRAM Timing
Code:
Intel i865PE DRAM Timing register 60h
BIT Description
1:0 DRAM RAS# Precharge (tRP)
00 = 4 DRAM clocks
01 = 3 DRAM clocks
10 = 2 DRAM clocks
11 = Reserved
3:2 DRAM RAS# to CAS# Delay (tRCD)
00 = 4 DRAM clocks
01 = 3 DRAM clocks
10 = 2 DRAM clocks
11 = Reserved
4 Burst Length
0 = 4 Clocks
1 = 8 Clocks
6:5 CAS# Latency (tCL)
00 = 2.5 DRAM clocks
01 = 2 DRAM clocks
10 = 3 DRAM clocks
11 = Reserved
9:7 Activate to Precharge delay (tRAS) Min
000 = 10 DRAM clocks
001 = 9 DRAM clocks
010 = 8 DRAM clocks
011 = 7 DRAM clocks
100 = 6 DRAM clocks
101 = 5 DRAM clocks
others = Reserved
10 Activate to Precharge Delay (tRAS) Max
0 = 120 micro-seconds
1 = 70 micro-seconds
Note: DDR333 DRAM requires a shorter tRAS (max) of 70 μs
12:11 Refresh Cycle Time (tRFC)
00 = 5
01 = 4
10 = 3
11 = 2
14:13 DRAM Idle Timer
00 = 64T
01 = 0T
10 = 8T
11 = 16T
20:16 Read Delay Adjust
00000 = disable
11111 = enable
24:21 Read Delay (tRD)
0000 = 11
0001 = 10
0010 = 9
0011 = 8
0100 = 7
0101 = 6
0110 = 5
0111 = 4
1000 = 3
1001 = 2
27:26 Read-Write Turnaround clocks
00 = 9
01 = 8
10 = 7
11 = 6
29:28 Write-Read Turnaround clocks
00 = 6
01 = 5
10 = 4
11 = 3
30 Write Recovery Time (tWR)
0 = 2
1 = 3
31 Write to Read Delay (tWTR)
0 = 1
1 = 2
DRAM Controller Mode
Code:
Intel i865PE DRAM Controller Mode register 68h
BIT Description
1:0 DRAM Type (DT)—RO. This field select between supported DRAM types.
00 = Reserved
01 = Dual data rate DRAM
Other = Reserved
6:4 Mode Select (SMS)—R/W. These bits select the special operational mode of the DRAM interface.
The special modes are intended for initialization at power up. Note that FCSEN (fast CS#) must be set
to 0 while SMS cycles are performed. It is expected that BIOS may program FCSEN to
possible 1 only after initialization.
000 = Post Reset state – When the MCH exits reset (power-up or otherwise), the mode select field is cleared to 000.
During any reset sequence, while power is applied and reset is active, the MCH de-asserts
all CKE signals. After internal reset is de-asserted, CKE signals remain de-asserted until
this field is written to a value different than 000. On this event, all CKE signals are asserted.
During suspend (S3, S4), MCH internal signal triggers DRAM controller to flush pending
commands and enter all rows into self-refresh mode. As part of resume sequence, the
MCH will be reset – which will clear this bit field to 000 and maintain CKE signals deasserted.
After internal reset is de-asserted, CKE signals remain de-asserted until this field
is written to a value different than 000. On this event, all CKE signals are asserted.
001 = NOP Command Enable – All processor cycles to DRAM result in a NOP command on the DRAM interface.
010 = All Banks Pre-charge Enable – All processor cycles to DRAM result in an “all banks precharge” command on the DRAM interface.
011 = Mode Register Set Enable – All processor cycles to DRAM result in a “mode register” set command on the DRAM interface. Host
address lines are mapped to DRAM address lines in order to specify the command sent. Host address HA[13:3] are mapped to
memory address SMA[5:1].
100 = Extended Mode Register Set Enable – All processor cycles to DRAM result in an “extended mode register set” command on the
DRAM interface. Host address lines are mapped to DRAM address lines in order to specify the command sent. Host address
lines are mapped to DRAM address lines in order to specify the command sent. Host address HA[13:3] are mapped to memory
address SMA[5:1].
101 = Reserved
110 = CBR Refresh Enable – In this mode all processor cycles to DRAM result in a CBR cycle on the DRAM interface
111 = Normal operation
10:8 Refresh Mode Select (RMS)—R/W. This field determines whether refresh is enabled and, if so, at
what rate refreshes will be executed.
000 = Reserved
001 = Refresh enabled. Refresh interval 15.6 μsec
010 = Refresh enabled. Refresh interval 7.8 μsec
011 = Refresh enabled. Refresh interval 64 μsec
111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode)
Other = Reserved
13 Command Per Clock (CPC)
0 = disable
1 = enable
14 Fast Chip Select (Performance Mode)
0 = disable
1 = enable
20 Dynamic Paging Mode
0 = disable
1 = enable (faster)
22:21 Number of Channels (CHAN)—R/W. The MCH memory controller supports three modes of operation.
When programmed for single-channel mode, there are three options: channel A is
populated, channel B is populated, or both are populated but not identically. When both channels
have DIMMs installed but they are not identical (from channel to channel), the controller operates
in a mode that is referred to as virtual single-channel. In this mode, the two physical channels are
not in lock step but act as one logical channel. To operate in either dual-channel mode, the two
channels must be populated identically.
00 = Single-channel or virtual single-channel
01 = Dual-channel, linear organization
10 = Dual-channel, tiled organization
11 = Reserved
29 Initialization Complete (IC)—R/W. This bit is used for communication of the software state
between the memory controller and the BIOS.
1 = BIOS sets this bit to 1 after initialization of the DRAM memory array is complete.
Dann gibt es noch zwei andere Einstellungen im BIOS:
PSB Parking (Bus parking)
Register b0d6f0 C0h [11]
1 =enable
0 =disable
PAT (MIB im BIOS)
Register b0d0f0 C4h [27]
1 = disable
0 = enable
Register b0d0f0 C4h [17:16]
10 = disable
01 = enable
Register b0d6f0 40h [20]
1 = disable
0 = enable
Register b0d6f0 40h [1:0]
11 = disable
00 = enable
[/CODE]
Warum der ganze Aufwand? Da wir jetzt diese Register Adressen kennen, könnte man ein Programm schreiben (option-rom), dass beim Systemstart diese Einstellungen umsetzt. Leider weiß ich noch nicht wie man mit dem Assembler den „Memory-Mapped I/O Register Space“ Addressiert, bzw. wie ich darin die Register umschreiben kann. Sollte aber funktionieren. Wenn Zeit und Lust da ist, werde ich das mal in Angriff nehmen.
edit. Korrektur
edit2. correction #2; see post
#330. thanks
@Antinomy
edit3. correction #3; see post
#333. thanks
@Antinomy