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Anmerkung: this_feature_currently_requires_accessing_site_using_safari
Ratio CMOS Setting: Auto
FSB Frequency: 400
CPU Clock Skew: Auto
NB Clock Skew: Auto
FSB Strap to North Bridge: 400
DRAM Frequency: DDR-800Mhz
DRAM CLK Skew on Channel A1: Auto
DRAM CLK Skew on Channel A2: Auto
DRAM CLK Skew on Channel B1: Auto
DRAM CLK Skew on Channel B2: Auto
DRAM Timing Control: Auto
1st Information: CAS# Latency: Auto DRAM RAS# to CAS# Delay: Auto DRAM RAS# Precharge: Auto DRAM RAS# Activate to Precharge: Auto RAS# to RAS# Delay: Auto Row Refresh Recycle Time: Auto Write Recovery Time: Auto Read to Precharge Time: Auto 2nd Information: Read to Write Delay (S/D): Auto Write to Read Delay (S): Auto Write to Read Delay (D): Auto Read to Read Delay (S): Auto Read to Read Delay (D): Auto Write to Write Delay (S): Auto Write to Write Delay (D): Auto 3rd Information: Write to PRE Delay: Auto Read to PRE Delay: Auto PRE to PRE Delay: Auto All PRE to ACT Delay: Auto All PRE to REF Delay: Auto DRAM Static Read Control: Auto DRAM Read Training: Auto MEM. OC Charger: Auto Ai Clock Twister: Auto
Ai Transaction Booster: Auto
Common Performance Level: Auto Pull-in of CHA PH1: Enabled Pull-in of CHA PH2: Enabled Pull-in of CHA PH3: Enabled Pull-in of CHB PH1: Enabled Pull-in of CHB PH2: Enabled Pull-in of CHB PH3: Enabled
PCIE Frequency: 100
CPU Voltage: 1.325
CPU PLL Voltage: 1.553
FSB Termination Voltage: 1.23
DRAM Voltage: 2.10
North Bridge Voltage: 1.19
South Bridge 1.5 Voltage: Auto
South Bridge 1.1 Voltage: Auto
CPU GTL Reference (0): Auto
CPU GTL Reference (1): Auto
CPU GTL Reference (2): Auto
CPU GTL Reference (3): Auto
NB GTL Reference: Auto
DDR2 ChA Reference Voltage: Auto
DDR2 ChB Reference Voltage: Auto
North Bridge DDR Reference: Auto
CPU Configuration:
Ratio CMOS Setting: 9 C1E Support: Diseable Max CPUID Value Limit: Disabled Intel Virtualization Tech: Enabled CPU TM Function: Diseable Execute Disable Bit: Enabled
Load-Line Calibration: Enabled
CPU Spread Spectrum: Auto
PCIE Spread Spectrum: Auto
Ratio CMOS Setting:9
FSB Frequency: 400
CPU Clock Skew: Auto
NB Clock Skew: Auto
FSB Strap to North Bridge: 400
DRAM Frequency: 1066
DRAM CLK Skew on Channel A1: Auto
DRAM CLK Skew on Channel A2: Auto
DRAM CLK Skew on Channel B1: Auto
DRAM CLK Skew on Channel B2: Auto
DRAM Timing Control: Manual
1st Information: CAS# Latency: 5
DRAM RAS# to CAS# Delay: 5
DRAM RAS# Precharge: 5
DRAM RAS# Activate to Precharge: 18
RAS# to RAS# Delay: Auto
Row Refresh Recycle Time: Auto
Write Recovery Time: Auto Read to Precharge Time: Auto
2nd Information: Read to Write Delay (S/D): Auto
Write to Read Delay (S): Auto
Write to Read Delay (D): Auto
Read to Read Delay (S): Auto
Read to Read Delay (D): Auto
Write to Write Delay (S): Auto
Write to Write Delay (D): Auto
3rd Information: Write to PRE Delay: Auto
Read to PRE Delay: Auto PRE to PRE Delay: Auto
All PRE to ACT Delay: Auto
All PRE to REF Delay: Auto
DRAM Static Read Control: Auto
DRAM Read Training: Auto
MEM. OC Charger: Auto
Ai Clock Twister: Auto
Ai Transaction Booster: Auto
Common Performance Level: Auto
Pull-in of CHA PH1: Deaktiviert
Pull-in of CHA PH2: Deaktiviert
Pull-in of CHA PH3: Deaktiviert
Pull-in of CHB PH1: Deaktiviert
Pull-in of CHB PH2: Deaktiviert
Pull-in of CHB PH3: Deaktiviert
PCIE Frequency: 100
CPU Voltage: 1.30 (evt.1.25v)
CPU PLL Voltage: 1.50
FSB Termination Voltage: 1.1(evt.1,15v)
DRAM Voltage: 2.1
North Bridge Voltage: 1.1(evt.1.15v)
South Bridge 1.5 Voltage: 1.5
South Bridge 1.1 Voltage: 1.1
CPU GTL Reference (0): Auto
CPU GTL Reference (1): Auto
CPU GTL Reference (2): Auto
CPU GTL Reference (3): Auto
NB GTL Reference: Auto
DDR2 ChA Reference Voltage: Auto
DDR2 ChB Reference Voltage: Auto
North Bridge DDR Reference: Auto
CPU Configuration:
Ratio CMOS Setting: 9 C1E Support: Deaktiviert
Max CPUID Value Limit: Disabled
Intel Virtualization Tech: Deaktiviert
CPU TM Function: Deaktiviert
Execute Disable Bit: Deaktiviert
Load-Line Calibration: Enabled
CPU Spread Spectrum: Deaktiviert
PCIE Spread Spectrum: Deaktiviert