[Sammelthread] Ryzen DDR5 RAM OC Thread

funkflix · Montag um 21:36

Letztendlich ja, hab selbst mal ein paar Tests gemacht:

[Sammelthread] - Ryzen DDR5 RAM OC Thread

Vergleichen Sie einen 16-Kern-Prozessor ohne 3D mit einem 8-Kern-Prozessor? Nicht schlecht.

www.hardwareluxx.de

[Sammelthread] - Ryzen DDR5 RAM OC Thread

Hat sich wer die 32GB Corsair Titanium 6000er CL30 bei Alternate bestellt?

www.hardwareluxx.de

Tatilica · Gestern um 09:10

funkflix schrieb:
Letztendlich ja, hab selbst mal ein paar Tests gemacht:

[Sammelthread] - Ryzen DDR5 RAM OC Thread

Vergleichen Sie einen 16-Kern-Prozessor ohne 3D mit einem 8-Kern-Prozessor? Nicht schlecht.

www.hardwareluxx.de

Hi guys, long time no see, done my own researches too with my little fellow X series & 8000+ mems 1:2 scenarios 🤓
As was found slighty improvements just but no real benefits due to tested all mine's raised Neo's mems freqs & put them in mirror, decided to stick with my first shoot 8000C36 GearOFF ... tightest timmings ever & shorter tFAW/WTRL/RDDL's combo 24/16/6/6/2 & tRTP/RDWR/WRRD 12/16/2 PBO full charge TDP 105W in Bios Enabled Limits 142/110/170 and 5,60ghz allcores, happy Merry Chrismas to you all Luxxer's here 🎆

Dragonheart69 · Gestern um 11:04

seppelchen schrieb:
@Dragonheart69 richtig, Taiphoon hält sich da aber bedeckt, daher meine Mutmaßung...

Danke und GN8

Nimm doch RAMON läuft sogar besser bei AM5 als Thaiphoon..👍

Gr3yh0und · Gestern um 14:53

6400 laufen soweit auch (2h anta, 1,5h 1usmus, 30k Karhu), Spannungen haben ich zum 8000er Setup initial erstmal gleich gelassen. SOC musste ich aber auf 1,225V hochdrehen.

Lexar Kit kam gerade auch.

Brain's City · Gestern um 18:08

@Tatilica You should align FCLK with the storage tact. So at 8000 -> 2000, 8100 -> 2050 and 8200 -> 2100. This runs Sycron and should then produce better results.

seppelchen · Heute um 00:10

Wenn die TM5 und Prime das bestätigen, wird das mein 24/7 Setting sein... Lediglich VSoc versuche ich noch zu senken.

Gr3yh0und · Heute um 09:21

@Vince96 Das Lexar Kit kam gestern abend vorbeigeflogen und sind auch 5600er mit 48ns. Selbe 6400er Timings laufen auf Anhieb mit 1,47VDD/1,35VDDQ/1,4VDDIO. Weniger als 1,45VDD wirft direkt Fehler.

RGB Software ist dieselbe wie von Gskill, nur anderes Logo drin. Ist also OEM.

RAMMon v3.3 Build: 1000 built with SysInfo v3.0 Build: 2001
PassMark (R) Software
www.passmark.com

============================
Memory settings
============================

Transfer rate: 6400 MT/s
Memory timings: 28-38-38-50
Channel mode: 2

============================
Memory capacity / benchmarks
============================

L1 cache: 80 KB (630.7 GB/s)
L2 cache: 1024 KB (123.8 GB/s)
L3 cache: 98304 KB (145.4 GB/s)
Physical RAM: 31.7 GB (38704 MB/s)
Latency: 41.664 ns

============================
Memory SPD information
============================
Item | Slot #1 | Slot #2 |
---------------------------------------------------------------------------------------------------------------|---------------------------------------------------------|---------------------------------------------------------|-
Ram Type | DDR5 | DDR5 |
Maximum Clock Speed (MHz) | 3200 (XMP) | 3200 (XMP) |
Maximum Transfer Speed (MT/s) | DDR5-6400 | DDR5-6400 |
Maximum Bandwidth (MB/s) | PC5-25600 | PC5-25600 |
Memory Capacity (MB) | 16384 | 16384 |
DIMM Temperature | N/A | N/A |
Jedec Manufacture Name | Lexar Co Limited | Lexar Co Limited |
Search Amazon.com | Search! | Search! |
SPD Revision | 1.0 | 1.0 |
Registered | No | No |
ECC | No | No |
On-Die ECC | Yes | Yes |
DIMM Slot # | 1 | 2 |
Manufactured | Week 40 of Year 2024 | Week 40 of Year 2024 |
Module Part # | LD5EU016G-6400LA | LD5EU016G-6400LA |
Module Revision | 0x0 | 0x0 |
Module Serial # | 6917129A (8a760024406917129a) | 69170537 (8a7600244069170537) |
Module Manufacturing Location | 0 | 0 |
# of Row Addressing Bits | 16 | 16 |
# of Column Addressing Bits | 10 | 10 |
# of Banks | 32 | 32 |
# of Ranks | 1 | 1 |
Device Width in Bits | 8 | 8 |
Bus Width in Bits | 32 | 32 |
Module Voltage | 1.1V | 1.1V |
CAS Latencies Supported | 22 26 28 30 32 36 40 42 46 50 | 22 26 28 30 32 36 40 42 46 50 |
Timings @ Max Frequency (JEDEC) | 46-45-45-90 | 46-45-45-90 |
Maximum frequency (MHz) | 2800 | 2800 |
Maximum Transfer Speed (MT/s) | DDR5-5600 | DDR5-5600 |
Maximum Bandwidth (MB/s) | PC5-22400 | PC5-22400 |
Minimum Clock Cycle Time, tCK (ns) | 0.357 | 0.357 |
Minimum CAS Latency Time, tAA (ns) | 16.000 | 16.000 |
Minimum RAS to CAS Delay, tRCD (ns) | 16.000 | 16.000 |
Minimum Row Precharge Time, tRP (ns) | 16.000 | 16.000 |
Minimum Active to Precharge Time, tRAS (ns) | 32.000 | 32.000 |
Minimum Row Active to Row Active Delay, tRRD (ns) | 0.000 | 0.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Time, tRC (ns) | 48.000 | 48.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC (ns) | 295.000 | 295.000 |
| | |
DDR5 Specific SPD Attributes | | |
Maximum Clock Cycle Time, tCKmax (ns) | 1.010 | 1.010 |
Write Recovery time (ns) | 30.000 | 30.000 |
Minimum Auto-Refresh to Active/Auto Refresh Command Period, tRFC2 (ns) | 160.000 | 160.000 |
Minimum Auto-Refresh to Active/Auto Refresh Command Period, tRFC4 (ns) | 130.000 | 130.000 |
Minimum Refresh Recovery Delay Time, tRFC1 (ns) | 0.000 | 0.000 |
Minimum Refresh Recovery Delay Time, tRFC2 (ns) | 0.000 | 0.000 |
Minimum Refresh Recovery Delay Time, tRFCsb (ns) | 0.000 | 0.000 |
Module Type | UDIMM | UDIMM |
Module information SPD revision | 1.0 | 1.0 |
SPD present | Yes | Yes |
SPD device type | SPD5118 | SPD5118 |
SPD Manufacturer | Montage Technology Group (Bank: 7, ID: 0x32) | Montage Technology Group (Bank: 7, ID: 0x32) |
PMIC 0 present | Yes | Yes |
PMIC 0 device type | PMIC5100 | PMIC5100 |
PMIC 0 Manufacturer | Global Mixed-mode Technology Inc (Bank: 14, ID: 0x85) | Global Mixed-mode Technology Inc (Bank: 14, ID: 0x85) |
PMIC 1 present | No | No |
PMIC 1 device type | | |
PMIC 1 Manufacturer | | |
PMIC 2 present | No | No |
PMIC 2 device type | | |
PMIC 2 Manufacturer | | |
Thermal Sensor 0 present | No | No |
Thermal Sensor 1 present | No | No |
Thermal Sensor device type | | |
Thermal Sensor Manufacturer | | |
Module Height (mm) | 32 | 32 |
Module Thickness Front (mm) | 2 | 2 |
Module Thickness Back (mm) | 1 | 1 |
Module Reference Card | Raw Card A Rev. 0 | Raw Card A Rev. 0 |
# DRAM Rows | 1 | 1 |
Heat spreader installed | No | No |
Operating Temperature Range | XT (0 to + 95 °C) | XT (0 to + 95 °C) |
Rank Mix | Symmetrical | Symmetrical |
Number of Package Ranks per Channel | 1 | 1 |
Number of Channels per DIMM | 2 | 2 |
Primary bus width per Channel | 32 bits | 32 bits |
Bus width extension per Channel | 0 bits | 0 bits |
DRAM Manufacture ID | 173 | 173 |
DRAM Manufacture Bank | 1 | 1 |
DRAM Manufacture Name | SK Hynix | SK Hynix |
DRAM Stepping | 4.1 | 4.1 |
SDRAM Package Type | Monolithic SDRAM | Monolithic SDRAM |
SDRAM Density Per Die | 16Gb | 16Gb |
SDRAM Bank Groups | 8 | 8 |
SDRAM Banks Per Bank Group | 4 | 4 |
Second SDRAM Package Type | | |
Second SDRAM Density Per Die | | |
Second SDRAM Column Address Bits | | |
Second SDRAM Row Address Bits | | |
Second SDRAM Device Width | | |
Second SDRAM Bank Groups | | |
Second SDRAM Banks Per Bank Group | | |
First SDRAM RFM RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) |
First SDRAM RFM RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) |
First SDRAM RFM Required | no | no |
First SDRAM RFM RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 |
Second SDRAM RFM RAAMMT | | |
Second SDRAM RFM RAAIMT | | |
Second SDRAM RFM Required | | |
Second SDRAM RFM RAA Counter Decrement per REF command | | |
First SDRAM ARFM Level A RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) |
First SDRAM ARFM Level A RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) |
First SDRAM ARFM Level A supported | no | no |
First SDRAM ARFM Level A RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 |
Second SDRAM ARFM Level A RAAMMT | | |
Second SDRAM ARFM Level A RAAIMT | | |
Second SDRAM ARFM Level A supported | | |
Second SDRAM ARFM Level A RAA Counter Decrement per REF command | | |
First SDRAM ARFM Level B RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) |
First SDRAM ARFM Level B RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) |
First SDRAM ARFM Level B supported | no | no |
First SDRAM ARFM Level B RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 |
Second SDRAM ARFM Level B RAAMMT | | |
Second SDRAM ARFM Level B RAAIMT | | |
Second SDRAM ARFM Level B supported | | |
Second SDRAM ARFM Level B RAA Counter Decrement per REF command | | |
First SDRAM ARFM Level C RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) |
First SDRAM ARFM Level C RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) |
First SDRAM ARFM Level C supported | no | no |
First SDRAM ARFM Level C RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 |
Second SDRAM ARFM Level C RAAMMT | | |
Second SDRAM ARFM Level C RAAIMT | | |
Second SDRAM ARFM Level C supported | | |
Second SDRAM ARFM Level C RAA Counter Decrement per REF command | | |
sPPR Granularity | bank | bank |
sPPR Undo/Lock | supported | supported |
Burst length 32 | supported | supported |
MBIST/mPPR | supported | supported |
mPPR/hPPR Abort | not supported | not supported |
PASR | supported | supported |
DCA Types Supported | Device supports DCA for 4-phase internal clock(s) | Device supports DCA for 4-phase internal clock(s) |
x4 RMW/ECS Writeback Suppression | supported | supported |
x4 RMW/ECS Writeback Suppression MR selector | MR9 | MR9 |
Bounded Fault | supported | supported |
SDRAM Nominal Voltage, VDDQ | 1.1V | 1.1V |
SDRAM Nominal Voltage, VPP | 1.8V | 1.8V |
Cyclical Redundancy Code (CRC) for Base Configuration | ac73 | ac73 |
| | |
XMP Attributes | | |
XMP version | 3.0 | 3.0 |
PMIC Vendor ID | 0D85 | 0D85 |
Number of PMICs on DIMM | 1 | 1 |
PMIC capabilities | | |
PMIC has capabilities for OC functions | Yes | Yes |
Current PMIC OC is enabled | Yes | Yes |
PMIC voltage default step size | 5mV | 5mV |
OC global reset functions | No | No |
Validation and Certification Capabilities | | |
DIMM is self-certified by DIMM vendor | No | No |
PMIC Component is validated by Intel AVL level | No | No |
XMP revision | 1.2 | 1.2 |
XMP Profile 1 | | |
Profile name | Profile 1 | Profile 1 |
XMP Certified | No | No |
Recommended number of DIMMs per channel | 1 | 1 |
Module VPP voltage | 1.80V | 1.80V |
Module VDD voltage | 1.40V | 1.40V |
Module VDDQ voltage | 1.40V | 1.40V |
Memory Controller voltage | 1.40V | 1.40V |
Clock speed (MHz) | 3200 | 3200 |
Transfer Speed (MT/s) | DDR5-6400 | DDR5-6400 |
Bandwidth (MB/s) | PC5-25600 | PC5-25600 |
Minimum clock cycle time, tCK (ns) | 0.312 | 0.312 |
Supported CAS latencies | 32 | 32 |
Minimum CAS latency time, tAA (ns) | 9.984 | 9.984 |
Minimum RAS to CAS delay time, tRCD (ns) | 11.856 | 11.856 |
Minimum row precharge time, tRP (ns) | 11.856 | 11.856 |
Minimum active to precharge time, tRAS (ns) | 23.712 | 23.712 |
Supported timing at highest clock speed | 32-38-38-76 | 32-38-38-76 |
Minimum Active to Auto-Refresh Delay, tRC (ns) | 35.568 | 35.568 |
Minimum Write Recovery Time, tWR (ns) | 30.000 | 30.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC1 (ns) | 295.000 | 295.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC2 (ns) | 160.000 | 160.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFCsb (ns) | 130.000 | 130.000 |
Minimum Read to Read Command Delay Time, Same Bank Group, tCCD_L (ns) | 5.000 (8 nCK) | 5.000 (8 nCK) |
Minimum Write to Write Command Delay Time, Same Bank Group, tCCD_L_WR (ns) | 20.000 (32 nCK) | 20.000 (32 nCK) |
Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group, tCCD_L_WR2 (ns) | 10.000 (16 nCK) | 10.000 (16 nCK) |
Minimum Write to Read Command Delay Time, Same Bank Group, tCCD_L_WTR (ns) | 10.000 (16 nCK) | 10.000 (16 nCK) |
Minimum Write to Read Command Delay Time, Different Bank Group, tCCD_S_WTR (ns) | 2.500 (4 nCK) | 2.500 (4 nCK) |
Minimum Active to Active Command Delay Time, Same Bank Group, tRRD_L (ns) | 5.000 (8 nCK) | 5.000 (8 nCK) |
Minimum Read to Precharge Command Delay Time, tRTP (ns) | 7.500 (12 nCK) | 7.500 (12 nCK) |
Minimum Four Activate Window, tFAW (ns) | 11.428 | 11.428 |
Advanced Memory Overclocking Features | | |
Real-Time Memory Frequency Overclocking | Supported | Supported |
Intel Dynamic Memory Boost | Supported | Supported |
System CMD Rate Mode | 2N | 2N |
Vendor Personality Byte | 0x00 | 0x00 |
| | |
EXPO Attributes | | |
EXPO version | 1.1 | 1.1 |
PMIC feature support | | |
PMIC 10 mV step size support | Yes | Yes |
EXPO Profile 1 | | |
DIMMs per channel supported | 1 | 1 |
EXPO Optional Block Support | | |
Block 1 enabled | Yes | Yes |
SDRAM VDD | 1.40V | 1.40V |
SDRAM VDDQ | 1.40V | 1.40V |
SDRAM VPP | 1.80V | 1.80V |
Clock speed (MHz) | 3200 | 3200 |
Transfer Speed (MT/s) | DDR5-6400 | DDR5-6400 |
Bandwidth (MB/s) | PC5-25600 | PC5-25600 |
Minimum clock cycle time, tCK (ns) | 0.312 | 0.312 |
Minimum CAS latency time, tAA (ns) | 9.984 | 9.984 |
Minimum RAS to CAS delay time, tRCD (ns) | 11.856 | 11.856 |
Minimum row precharge time, tRP (ns) | 11.856 | 11.856 |
Minimum active to precharge time, tRAS (ns) | 23.712 | 23.712 |
Supported timing at highest clock speed | 32-38-38-76 | 32-38-38-76 |
Minimum Active to Auto-Refresh Delay, tRC (ns) | 35.568 | 35.568 |
Minimum Write Recovery Time, tWR (ns) | 30.000 | 30.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC1 (ns) | 295.000 | 295.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC2 (ns) | 160.000 | 160.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFCsb (ns) | 130.000 | 130.000 |
Minimum Active to Active Command Delay Time, Same Bank Group, tRRD_L (ns) | 5.000 | 5.000 |
Minimum Read to Read Command Delay Time, Same Bank Group, tCCD_L (ns) | 5.000 | 5.000 |
Minimum Write to Write Command Delay Time, Same Bank Group, tCCD_L_WR (ns) | 20.000 | 20.000 |
Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group, tCCD_L_WR2 (ns) | 10.000 | 10.000 |
Minimum Four Activate Window, tFAW (ns) | 11.428 | 11.428 |
Minimum Write to Read Command Delay Time, Same Bank Group, tWTR_L (ns) | 10.000 | 10.000 |
Minimum Write to Read Command Delay Time, Different Bank Group, tWTR_S (ns) | 2.500 | 2.500 |
Minimum Read to Precharge Command Delay Time, tRTP (ns) | 7.500 | 7.500 |

RedF · Heute um 10:10

Sehr gutes Bin.
Minimum Auto-Refresh to Active/Auto-Refresh Time, tRC (ns) 48.000

Ich habe "nur" 48,428

zwerg-05 · Heute um 10:11

Mal ne frage wie testet mann am besten ram habe jetzt 4*16gb drin corsair titanium laufen auf Anhieb mit Expo Profile auf 6000 memtest läuft bis jetzt ohne fehler

RedF · Heute um 10:17

zwerg-05 schrieb:
Mal ne frage wie testet mann am besten ram habe jetzt 4*16gb drin corsair titanium laufen auf Anhieb mit Expo Profile auf 6000 memtest läuft bis jetzt ohne fehler

Entweder Karhu bis 10000% (oder 8K% oder 20K% da scheiden sich die geister), Testmem 5 mit Anta777 Extreme oder mit Prime95 Large FFT AVX.

zwerg-05 · Heute um 10:23

Okay werde ich mal testen aber finde 6000mhz bei 4 RAM riegel ist schon gut

So prime95 läuft seit gut 15 Minuten wie lange sollte man denn laufen lassen?

Chris1975 · Heute um 10:51

2-3h wären mal ein anfang da passieren erfahrungsgemäß die meisten Fehler auch wegen z.b Temperatur.

zwerg-05 · Heute um 11:04

Temperatur sehen sehr gut aus ram max 62° läuft nun schon 40 Minuten ohne Fehler also 4*16gb auf 6000mhz wäre schon echt top denke ich

Pinius · Heute um 11:21

Gibt es schon auf den Markt gute 2x32GB RAMs die PC6000 Cl28 machen auf AM5 System.

Chris1975 · Heute um 11:47

Wenn alle so ticken würden wie die meisten hier wäre Expo nur ne Randnotiz. A oder M Die und das Binning mehr braucht man nicht zu wissen der Rest wird am lebenden Objekt ermittelt.

zwerg-05 · Heute um 12:14

also denke expo 6000 mit 4*16gb laufen stabil jetzt die tage mal die timings ausloten
Muss sagen das ich mit den corsair dominator titanium Expo 6000 echt zufrieden bin sind echt gute speicher

LuxSkywalker · Heute um 12:38

@zwerg-05

hast du mal einen aktuellen ZenTiming Screenshot davon?

zwerg-05 · Heute um 12:48

hier bitte was kann mann denn noch optiemieren?

wie gesagt ist im moment nur expo 2 geladen

seppelchen · Heute um 14:34

RFC, evtl. VSoc, REFI... setzt dich bitte mit der Liste von Seite 1 auseinander. Am Anfang vllt. verwirrend, aber ungemein hilfreich. Ich habe meine 7200er Lexar damit stabil ausreizen können und auch das jetzige Adata 48GB Kit läuft nun stabil mit seinem 24/7 Setup.

LuxSkywalker · Heute um 15:08

zwerg-05 schrieb:
hier bitte was kann mann denn noch optiemieren?
...

einfach alles :asthanos:

wie @seppelchen schon geschrieben hat einfach mit der Excel Liste anfangen

Vince96 · Vor 30 Minuten

Gr3yh0und schrieb:
@Vince96 Das Lexar Kit kam gestern abend vorbeigeflogen und sind auch 5600er mit 48ns. Selbe 6400er Timings laufen auf Anhieb mit 1,47VDD/1,35VDDQ/1,4VDDIO. Weniger als 1,45VDD wirft direkt Fehler.

RGB Software ist dieselbe wie von Gskill, nur anderes Logo drin. Ist also OEM.

RAMMon v3.3 Build: 1000 built with SysInfo v3.0 Build: 2001
PassMark (R) Software
www.passmark.com

============================
Memory settings
============================

Transfer rate: 6400 MT/s
Memory timings: 28-38-38-50
Channel mode: 2

============================
Memory capacity / benchmarks
============================

L1 cache: 80 KB (630.7 GB/s)
L2 cache: 1024 KB (123.8 GB/s)
L3 cache: 98304 KB (145.4 GB/s)
Physical RAM: 31.7 GB (38704 MB/s)
Latency: 41.664 ns

============================
Memory SPD information
============================
Item | Slot #1 | Slot #2 |
---------------------------------------------------------------------------------------------------------------|---------------------------------------------------------|---------------------------------------------------------|-
Ram Type | DDR5 | DDR5 |
Maximum Clock Speed (MHz) | 3200 (XMP) | 3200 (XMP) |
Maximum Transfer Speed (MT/s) | DDR5-6400 | DDR5-6400 |
Maximum Bandwidth (MB/s) | PC5-25600 | PC5-25600 |
Memory Capacity (MB) | 16384 | 16384 |
DIMM Temperature | N/A | N/A |
Jedec Manufacture Name | Lexar Co Limited | Lexar Co Limited |
Search Amazon.com | Search! | Search! |
SPD Revision | 1.0 | 1.0 |
Registered | No | No |
ECC | No | No |
On-Die ECC | Yes | Yes |
DIMM Slot # | 1 | 2 |
Manufactured | Week 40 of Year 2024 | Week 40 of Year 2024 |
Module Part # | LD5EU016G-6400LA | LD5EU016G-6400LA |
Module Revision | 0x0 | 0x0 |
Module Serial # | 6917129A (8a760024406917129a) | 69170537 (8a7600244069170537) |
Module Manufacturing Location | 0 | 0 |
# of Row Addressing Bits | 16 | 16 |
# of Column Addressing Bits | 10 | 10 |
# of Banks | 32 | 32 |
# of Ranks | 1 | 1 |
Device Width in Bits | 8 | 8 |
Bus Width in Bits | 32 | 32 |
Module Voltage | 1.1V | 1.1V |
CAS Latencies Supported | 22 26 28 30 32 36 40 42 46 50 | 22 26 28 30 32 36 40 42 46 50 |
Timings @ Max Frequency (JEDEC) | 46-45-45-90 | 46-45-45-90 |
Maximum frequency (MHz) | 2800 | 2800 |
Maximum Transfer Speed (MT/s) | DDR5-5600 | DDR5-5600 |
Maximum Bandwidth (MB/s) | PC5-22400 | PC5-22400 |
Minimum Clock Cycle Time, tCK (ns) | 0.357 | 0.357 |
Minimum CAS Latency Time, tAA (ns) | 16.000 | 16.000 |
Minimum RAS to CAS Delay, tRCD (ns) | 16.000 | 16.000 |
Minimum Row Precharge Time, tRP (ns) | 16.000 | 16.000 |
Minimum Active to Precharge Time, tRAS (ns) | 32.000 | 32.000 |
Minimum Row Active to Row Active Delay, tRRD (ns) | 0.000 | 0.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Time, tRC (ns) | 48.000 | 48.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC (ns) | 295.000 | 295.000 |
| | |
DDR5 Specific SPD Attributes | | |
Maximum Clock Cycle Time, tCKmax (ns) | 1.010 | 1.010 |
Write Recovery time (ns) | 30.000 | 30.000 |
Minimum Auto-Refresh to Active/Auto Refresh Command Period, tRFC2 (ns) | 160.000 | 160.000 |
Minimum Auto-Refresh to Active/Auto Refresh Command Period, tRFC4 (ns) | 130.000 | 130.000 |
Minimum Refresh Recovery Delay Time, tRFC1 (ns) | 0.000 | 0.000 |
Minimum Refresh Recovery Delay Time, tRFC2 (ns) | 0.000 | 0.000 |
Minimum Refresh Recovery Delay Time, tRFCsb (ns) | 0.000 | 0.000 |
Module Type | UDIMM | UDIMM |
Module information SPD revision | 1.0 | 1.0 |
SPD present | Yes | Yes |
SPD device type | SPD5118 | SPD5118 |
SPD Manufacturer | Montage Technology Group (Bank: 7, ID: 0x32) | Montage Technology Group (Bank: 7, ID: 0x32) |
PMIC 0 present | Yes | Yes |
PMIC 0 device type | PMIC5100 | PMIC5100 |
PMIC 0 Manufacturer | Global Mixed-mode Technology Inc (Bank: 14, ID: 0x85) | Global Mixed-mode Technology Inc (Bank: 14, ID: 0x85) |
PMIC 1 present | No | No |
PMIC 1 device type | | |
PMIC 1 Manufacturer | | |
PMIC 2 present | No | No |
PMIC 2 device type | | |
PMIC 2 Manufacturer | | |
Thermal Sensor 0 present | No | No |
Thermal Sensor 1 present | No | No |
Thermal Sensor device type | | |
Thermal Sensor Manufacturer | | |
Module Height (mm) | 32 | 32 |
Module Thickness Front (mm) | 2 | 2 |
Module Thickness Back (mm) | 1 | 1 |
Module Reference Card | Raw Card A Rev. 0 | Raw Card A Rev. 0 |
# DRAM Rows | 1 | 1 |
Heat spreader installed | No | No |
Operating Temperature Range | XT (0 to + 95 °C) | XT (0 to + 95 °C) |
Rank Mix | Symmetrical | Symmetrical |
Number of Package Ranks per Channel | 1 | 1 |
Number of Channels per DIMM | 2 | 2 |
Primary bus width per Channel | 32 bits | 32 bits |
Bus width extension per Channel | 0 bits | 0 bits |
DRAM Manufacture ID | 173 | 173 |
DRAM Manufacture Bank | 1 | 1 |
DRAM Manufacture Name | SK Hynix | SK Hynix |
DRAM Stepping | 4.1 | 4.1 |
SDRAM Package Type | Monolithic SDRAM | Monolithic SDRAM |
SDRAM Density Per Die | 16Gb | 16Gb |
SDRAM Bank Groups | 8 | 8 |
SDRAM Banks Per Bank Group | 4 | 4 |
Second SDRAM Package Type | | |
Second SDRAM Density Per Die | | |
Second SDRAM Column Address Bits | | |
Second SDRAM Row Address Bits | | |
Second SDRAM Device Width | | |
Second SDRAM Bank Groups | | |
Second SDRAM Banks Per Bank Group | | |
First SDRAM RFM RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) |
First SDRAM RFM RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) |
First SDRAM RFM Required | no | no |
First SDRAM RFM RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 |
Second SDRAM RFM RAAMMT | | |
Second SDRAM RFM RAAIMT | | |
Second SDRAM RFM Required | | |
Second SDRAM RFM RAA Counter Decrement per REF command | | |
First SDRAM ARFM Level A RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) |
First SDRAM ARFM Level A RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) |
First SDRAM ARFM Level A supported | no | no |
First SDRAM ARFM Level A RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 |
Second SDRAM ARFM Level A RAAMMT | | |
Second SDRAM ARFM Level A RAAIMT | | |
Second SDRAM ARFM Level A supported | | |
Second SDRAM ARFM Level A RAA Counter Decrement per REF command | | |
First SDRAM ARFM Level B RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) |
First SDRAM ARFM Level B RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) |
First SDRAM ARFM Level B supported | no | no |
First SDRAM ARFM Level B RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 |
Second SDRAM ARFM Level B RAAMMT | | |
Second SDRAM ARFM Level B RAAIMT | | |
Second SDRAM ARFM Level B supported | | |
Second SDRAM ARFM Level B RAA Counter Decrement per REF command | | |
First SDRAM ARFM Level C RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) |
First SDRAM ARFM Level C RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) |
First SDRAM ARFM Level C supported | no | no |
First SDRAM ARFM Level C RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 |
Second SDRAM ARFM Level C RAAMMT | | |
Second SDRAM ARFM Level C RAAIMT | | |
Second SDRAM ARFM Level C supported | | |
Second SDRAM ARFM Level C RAA Counter Decrement per REF command | | |
sPPR Granularity | bank | bank |
sPPR Undo/Lock | supported | supported |
Burst length 32 | supported | supported |
MBIST/mPPR | supported | supported |
mPPR/hPPR Abort | not supported | not supported |
PASR | supported | supported |
DCA Types Supported | Device supports DCA for 4-phase internal clock(s) | Device supports DCA for 4-phase internal clock(s) |
x4 RMW/ECS Writeback Suppression | supported | supported |
x4 RMW/ECS Writeback Suppression MR selector | MR9 | MR9 |
Bounded Fault | supported | supported |
SDRAM Nominal Voltage, VDDQ | 1.1V | 1.1V |
SDRAM Nominal Voltage, VPP | 1.8V | 1.8V |
Cyclical Redundancy Code (CRC) for Base Configuration | ac73 | ac73 |
| | |
XMP Attributes | | |
XMP version | 3.0 | 3.0 |
PMIC Vendor ID | 0D85 | 0D85 |
Number of PMICs on DIMM | 1 | 1 |
PMIC capabilities | | |
PMIC has capabilities for OC functions | Yes | Yes |
Current PMIC OC is enabled | Yes | Yes |
PMIC voltage default step size | 5mV | 5mV |
OC global reset functions | No | No |
Validation and Certification Capabilities | | |
DIMM is self-certified by DIMM vendor | No | No |
PMIC Component is validated by Intel AVL level | No | No |
XMP revision | 1.2 | 1.2 |
XMP Profile 1 | | |
Profile name | Profile 1 | Profile 1 |
XMP Certified | No | No |
Recommended number of DIMMs per channel | 1 | 1 |
Module VPP voltage | 1.80V | 1.80V |
Module VDD voltage | 1.40V | 1.40V |
Module VDDQ voltage | 1.40V | 1.40V |
Memory Controller voltage | 1.40V | 1.40V |
Clock speed (MHz) | 3200 | 3200 |
Transfer Speed (MT/s) | DDR5-6400 | DDR5-6400 |
Bandwidth (MB/s) | PC5-25600 | PC5-25600 |
Minimum clock cycle time, tCK (ns) | 0.312 | 0.312 |
Supported CAS latencies | 32 | 32 |
Minimum CAS latency time, tAA (ns) | 9.984 | 9.984 |
Minimum RAS to CAS delay time, tRCD (ns) | 11.856 | 11.856 |
Minimum row precharge time, tRP (ns) | 11.856 | 11.856 |
Minimum active to precharge time, tRAS (ns) | 23.712 | 23.712 |
Supported timing at highest clock speed | 32-38-38-76 | 32-38-38-76 |
Minimum Active to Auto-Refresh Delay, tRC (ns) | 35.568 | 35.568 |
Minimum Write Recovery Time, tWR (ns) | 30.000 | 30.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC1 (ns) | 295.000 | 295.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC2 (ns) | 160.000 | 160.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFCsb (ns) | 130.000 | 130.000 |
Minimum Read to Read Command Delay Time, Same Bank Group, tCCD_L (ns) | 5.000 (8 nCK) | 5.000 (8 nCK) |
Minimum Write to Write Command Delay Time, Same Bank Group, tCCD_L_WR (ns) | 20.000 (32 nCK) | 20.000 (32 nCK) |
Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group, tCCD_L_WR2 (ns) | 10.000 (16 nCK) | 10.000 (16 nCK) |
Minimum Write to Read Command Delay Time, Same Bank Group, tCCD_L_WTR (ns) | 10.000 (16 nCK) | 10.000 (16 nCK) |
Minimum Write to Read Command Delay Time, Different Bank Group, tCCD_S_WTR (ns) | 2.500 (4 nCK) | 2.500 (4 nCK) |
Minimum Active to Active Command Delay Time, Same Bank Group, tRRD_L (ns) | 5.000 (8 nCK) | 5.000 (8 nCK) |
Minimum Read to Precharge Command Delay Time, tRTP (ns) | 7.500 (12 nCK) | 7.500 (12 nCK) |
Minimum Four Activate Window, tFAW (ns) | 11.428 | 11.428 |
Advanced Memory Overclocking Features | | |
Real-Time Memory Frequency Overclocking | Supported | Supported |
Intel Dynamic Memory Boost | Supported | Supported |
System CMD Rate Mode | 2N | 2N |
Vendor Personality Byte | 0x00 | 0x00 |
| | |
EXPO Attributes | | |
EXPO version | 1.1 | 1.1 |
PMIC feature support | | |
PMIC 10 mV step size support | Yes | Yes |
EXPO Profile 1 | | |
DIMMs per channel supported | 1 | 1 |
EXPO Optional Block Support | | |
Block 1 enabled | Yes | Yes |
SDRAM VDD | 1.40V | 1.40V |
SDRAM VDDQ | 1.40V | 1.40V |
SDRAM VPP | 1.80V | 1.80V |
Clock speed (MHz) | 3200 | 3200 |
Transfer Speed (MT/s) | DDR5-6400 | DDR5-6400 |
Bandwidth (MB/s) | PC5-25600 | PC5-25600 |
Minimum clock cycle time, tCK (ns) | 0.312 | 0.312 |
Minimum CAS latency time, tAA (ns) | 9.984 | 9.984 |
Minimum RAS to CAS delay time, tRCD (ns) | 11.856 | 11.856 |
Minimum row precharge time, tRP (ns) | 11.856 | 11.856 |
Minimum active to precharge time, tRAS (ns) | 23.712 | 23.712 |
Supported timing at highest clock speed | 32-38-38-76 | 32-38-38-76 |
Minimum Active to Auto-Refresh Delay, tRC (ns) | 35.568 | 35.568 |
Minimum Write Recovery Time, tWR (ns) | 30.000 | 30.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC1 (ns) | 295.000 | 295.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC2 (ns) | 160.000 | 160.000 |
Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFCsb (ns) | 130.000 | 130.000 |
Minimum Active to Active Command Delay Time, Same Bank Group, tRRD_L (ns) | 5.000 | 5.000 |
Minimum Read to Read Command Delay Time, Same Bank Group, tCCD_L (ns) | 5.000 | 5.000 |
Minimum Write to Write Command Delay Time, Same Bank Group, tCCD_L_WR (ns) | 20.000 | 20.000 |
Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group, tCCD_L_WR2 (ns) | 10.000 | 10.000 |
Minimum Four Activate Window, tFAW (ns) | 11.428 | 11.428 |
Minimum Write to Read Command Delay Time, Same Bank Group, tWTR_L (ns) | 10.000 | 10.000 |
Minimum Write to Read Command Delay Time, Different Bank Group, tWTR_S (ns) | 2.500 | 2.500 |
Minimum Read to Precharge Command Delay Time, tRTP (ns) | 7.500 | 7.500 |

Bei Lexar weiß man halt nicht was man bekommt. Manchmal 4800er oder 5600er.

Jedes Kit verhält sich anders. Das Lexar Kit braucht am 7950x3D etwa 0,3V mehr VDD als auf dem 7800x3D.
Die 5600B sind glaub immer Class V A-Die

zwerg-05 · Vor 21 Minuten

Ich Blick da nicht durch habe ne Latenz vo 150ns das kann doch nicht sein

[Sammelthread] Ryzen DDR5 RAM OC Thread

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