@Veii
random questions while i'm here before work if you don't mind answering when you have some extra time:
- if I set ICCMAX to 400a do I set anything else as in like 253 power limit or leave unlimited? and I saw don't use fixed clock/voltages which I personally do not but anything else I should/shouldnt use with ICCMAX
This is complicated for me to answer.
Honestly i'm uncertain.
Because looking at the latest Intel-decided powertargets for 14th gen,
and "making questionable unofficial recommenations now global recommendations"
^ see igorslabs breakdown on the 14th gen specification and changes.
I ... don't know? Ya, something like this.
My personal experience messing with dynamic AMD gear would say
~ that having a PL2 (short/burst powerlimit) not only is good for the PSU combating transient spikes
~ but also is some sort of free performance uplift/cheatery - because Wattage is only calculated in a 1h time base.
Soo given rounding and ramp time, short-term wattage limiter may not be such of a bad idea
~ while long term PL1 powerlimiter, should rather be a powersupply focused limiter.
Thermal throttle then is what bridges the (perf *) gap , as long as silicon was designed with such in mind.
* because powerlimiters are usually emergency throttles and do cause bad performance or even stutter scenarios.
~ same as TJMAX throttles ~ hence we have several types of thermal limiters too.
A ramp-time x hold-time topic.
But all of this is thrown out of the window with the specifications or so to say "extended extreme" (hah) targets for their XtremePowerProfile.
PL1 & PL2 match, and ICCMAX is just ICCMAX ~ PL4.
Given i'm nowhere near classified enough to talk about their substrate design and lack insight on their (Intel) manufacturing
I can not even imagine what would be the a good thermal/duration/loadtype - limiter for ICCMAX. When to extend it beyond~
Intel decides this is 400A for 14th gen & they don't publish specification on CPUs that will degrade in 1 year ~ so 400A it is
I/we haven't seen a need for a powerlimiter anymore, when we have ICCMAX.
But i can be wrong and i do think that a healthy combination of PL2 + PL4 is better.
PL2 being ~27-30W above your Target Powerlimiter (PL1). Guessed-estimate.
A friend does recommend 320A (288W) for 13th gen and keeps the recommendation up for 14th gen.
I , kind of understand the recommendation reason ~ especially from a SystemIntegrator.
But the math doesn't add up to me, as that is ~348W PL2, this ICCMAX. This includes gathered knowledge of changed thermal-target with KS+14th gen.
Eh, everyone cooks differently and the only anchorpoint i can have is intel's target.
How good or maybe concerning, it sounds. Soo 400A it is.
🤭
- if I have a good cpu in terms of overall SP, do I still mess with the v/f curve at all since I don't think mine is leaky? is something like this worth doing on a good sp cpu or? and what am I aiming for in terms of looks for the curve?
The reason to mess with V/F is soo general headroom increases. // You can't control IMC upkeep voltage. But influence margins.
Given several clock's are connected and everything is loadbalanced ~ based on V/F curve
Given SA VID & UncoreVID play a critical role here (under the surface)
I would say ~ yes
A healthy mixture of linear dropping AC_LL (0.6 is a good starting point)
And a more substrate focused personal V/F.
Should be helpful to stay bellow the internal voltage limiters ~ which do track VID.
Some CPUs do come out of Lab with a sub 1.4 VID curve.
But this luxury doesnt work of every sample. // Especially as they target 105°c stability for SKUs clock-targets.
// Soo, many samples need the higher voltage, as they become leakier ~ yet no low-thermal foldoverpoint like it was mid 2015 at Skylake era.
Like above ~ while being slightly educated on now couple substrate behaviors (GloFo-14, GloFo-12, GloFo-12+, TSMC-7n)
I just had a recent Intel CPU for a very limited time.
~90 days.
A luxury time, vs the usually max-borrowed 30 days
But far too little, to dig deeper.
I'm sorry, for not being very helpful here.
- any idea if I should mess with SA PLL Frequency at all or leave auto? seen a couple people use it at 3200 but I can't find much good info on it at all
SA/SOC Freq matters for BLCK change
But , there was no need to mess with it.
Generally no PLL unless subzero or basically non existent margins
8600++
Its very suboptimal to touch PLL, vs just work with the voltage itself.
PLL limits max voltage range.
and what am I aiming for in terms of looks for the
Please read the posts from zebra_hun & tibcsi , over here.
Its about last 10 pages or 12.
I dont know how to summerize and compact it any further. Sorry
- if I were to use TVB with ICCMAX should I be going after a certain loadline to tune with or? current setup uses LLC6 but mostly because I haven't really tuned/messed with it since I had it working good last
Up to Board
One uses LLC 4, one stays at LLC3 that is default
Up to Board.
If you mean on the leaky/non-leaky topic.
mmm, complicated
🤭
because of the many variables. I wish i could answer it easier.
Try it out~
V/F tuning by itself is algorithmic.
At whatever LLC you run it, even if Vout will differ. The behavior will stay the same
LLC will change AC_LL minimums and targets. But more than that, barely.
It has thermal affectness too and noise , soo not bothering with it and trusting Boardengineer is rather the path to take
But outside of that SNR topic ~ its nearly linear.
Soo it will not be your worry when shaping V/F.
Now how substrate behaves
at which frequency point its more efficient
and what sort of droop amount it needs for this freq point, including factored AVX(2)/FMA offset
Eh , too many variables soo "its complicated, sorry".
Especially as my posts are already very big. Even with all linebreaks to easen topics.
Learn by trying
