[Sammelthread] Intel DDR5 RAM OC Thread

I will try that, but unfortunately got error 4 very soon.
Anhang anzeigen 964668


It will be due to the lowered MC I believe.

I will raise the RAM VDD and MC in next try, but I have to finish testing for today.
The fun just began. :(
#4 is nearly always DIMM PCB crash
Its a very low chance to be like a #0 that can be shroedingers signal
One time its hard dropout, one time its dropout due to overvoltage :)

#4 chance is very high that dimm pcbs crash due to no delta on VDDQ_MEM.
And RTTs being tuned how they are tuned.

Go -90mV maybe before starting
We need a clean TM5 before tracking y-cruncher.
And a y-cruncher that doesnt hard fail in first 1-2 loops, before tracking TM5
Else both will bother each and report wrong errors.
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Alright :)
Until next time
Im out now too~
 
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#4 is almost always DIMM PCB crash
Its a very low chance to be like a #0 that can be shroedingers signal
One time its hard dropout, one time its dropout due to overvoltage:)

#4 chance is very high that dimm pcbs crash due to no delta on VDDQ_MEM.
And RTTs being tuned how they are tuned.

Go -90mV maybe before starting
We need a clean TM5 before tracking y-cruncher.
And a y-cruncher that doesn't fail hard in first 1-2 loops, before tracking TM5
Else both will bother each and report wrong errors.
Beitrag automatisch zusammengeführt:

Alright:)
Until next time
Im out now too~
Thank you. Progress is slow, but the result is more important. 😊
 
I found some free time to start from the start again. Since i couldn't get reboot stable 8000 no matter what i got 7800 stable to have a starting point at least .
Bios settings, anything lower and i fail VST/VT3. Reboot-cold boot-psu off/on stable
All auto
VDDQ Training Enabled
VDD/VDDQ 1.47/1.41
TX 1.29
IMC 1.38
SA 1.17
Veii7800.png


Then i tried 8000 again but was not reboot stable, maybe i have a weak CPU IMC and should give up?
All Auto, Tweak Mode Auto

8K_YCooler.png
 
I found some free time to start from the start again. Since i couldn't get reboot stable 8000 no matter what i got 7800 stable to have a starting point at least .
Bios settings, anything lower and i fail VST/VT3. Reboot-cold boot-psu off/on stable
All auto
VDDQ Training Enabled
VDD/VDDQ 1.47/1.41
TX 1.29
IMC 1.38
SA 1.17
Anhang anzeigen 964734

Then i tried 8000 again but was not reboot stable, maybe i have a weak CPU IMC and should give up?
All Auto, Tweak Mode Auto

Anhang anzeigen 964735
A few things I don't understand.
Why are you doing such short tests?
The 7800MHz profile gives a nice VT3 speed, but the 8000MHz profile gives a much worse VT3.
Is VDDQ Training Enabled and is the voltage entered manually?
I turn it off and give it a value so don't get confused. Of course I could be wrong, I'm not a pro oc'er.
I would give the RRD-L value a 12, not an 8.
I think RTP/WR can still go to 8000MHz on 12/24. (2x16Gb)
WTR_L/S I use 24/8 in BIOS.
For this I need 1.51/1.48V VDD/Q.
TM5 runs the 25 rounds at the lower voltage, but Y does not.
As I wrote, I'm not a pro, but if you post longer tests and include a possible TM5 error, you'll get better help from others.
 
VDDQ Training Enabled
Off
maybe i have a weak CPU IMC and should give up?
How many tries did you attempt before deciding to give up ?
Just asking :-)
VDDQ 1.47/1.41
TX 1.29
VDDQ_CPU (TX IVR) 1.19v.
// Target value is near 1.18-1.21v depends on your V/F Curve.
Voltage/preset you used is for 24gb kits.
Start at 7800 profile and rerun y-cruncher

PSU off-boot after VDDQ Training off.
MRC "Memory Context Restore" ~ off.

ICCMAX limit to 320A
KS would be higher. KF is 13th gen yield.

If IA_AC is bellow 0.5 , remove this offset.


Morning~
 
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Off

VDDQ_CPU (TX IVR) 1.19v.
// Target value is near 1.18-1.21v depends on your V/F Curve.
Voltage/preset you used is for 24gb kits.
Start at 7800 profile and rerun y-cruncher

PSU off-boot after VDDQ Training off.
MRC "Memory Context Restore" ~ off.

ICCMAX limit to 320A
KS would be higher. KF is 13th gen yield.

If IA_AC is bellow 0.5 , remove this offset.

Morning~
Good morning to you too...
I'm so sorry I was sleepy last night, the values I posted are with VDDQ Training - disabled.

MRC "Memory Context Restore" is MRC fast boot? If so I also have that disabled.

I will try TX 1.19 and iccmax 320 when I get back home.
AC_LL is set at 0.05 now. I will try auto too.
 
A few things I don't understand.
Why are you doing such short tests?

Is VDDQ Training Enabled and is the voltage entered manually?
For this I need 1.51/1.48V VDD/Q.
TM5 runs the 25 rounds at the lower voltage, but Y does not.
As I wrote, I'm not a pro, but if you post longer tests and include a possible TM5 error, you'll get better help from others.
Because I don't have much free time to test for hours. And I also only use my pc for browsing/gaming. When/if I manage to get 8000 reboot stable for at least 10 loops then I will test for longer.
As I said VDDQ Training is disabled.
On TM5 I get no errors that's why I didn't post it.
Another guy also posted in OCnet that he needed more VDD to pass ycruncher. Maybe I also have to try that.
 
90min is the target
45-90min, but 90min is a good value.
For any Hardware-part basically.

Usually, if you want to be sure your settings are correct
You test for several hours. Laws of physics are unforgiving & level of correction is equally sophisticated :)

And because one tests long, you need an ICCMAX limiter.
// Not all Boardpartners follow it. Often its set very high, but parts of the CPU still hit it.
Fixed voltage is forbidden and fixed clock is forbidden.
Well, that is if one cares about their lifetime of the CPU :-)
 
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@Veii

random questions while i'm here before work if you don't mind answering when you have some extra time:

- if I set ICCMAX to 400a do I set anything else as in like 253 power limit or leave unlimited? and I saw don't use fixed clock/voltages which I personally do not but anything else I should/shouldnt use with ICCMAX

- if I have a good cpu in terms of overall SP, do I still mess with the v/f curve at all since I don't think mine is leaky? is something like this worth doing on a good sp cpu or? and what am I aiming for in terms of looks for the curve?

- any idea if I should mess with SA PLL Frequency at all or leave auto? seen a couple people use it at 3200 but I can't find much good info on it at all

- if I were to use TVB with ICCMAX should I be going after a certain loadline to tune with or? current setup uses LLC6 but mostly because I haven't really tuned/messed with it since I had it working good last
 
@Veii

random questions while i'm here before work if you don't mind answering when you have some extra time:

- if I set ICCMAX to 400a do I set anything else as in like 253 power limit or leave unlimited? and I saw don't use fixed clock/voltages which I personally do not but anything else I should/shouldnt use with ICCMAX
This is complicated for me to answer.
Honestly i'm uncertain.
Because looking at the latest Intel-decided powertargets for 14th gen,
and "making questionable unofficial recommenations now global recommendations"
^ see igorslabs breakdown on the 14th gen specification and changes.

I ... don't know? Ya, something like this.

My personal experience messing with dynamic AMD gear would say
~ that having a PL2 (short/burst powerlimit) not only is good for the PSU combating transient spikes
~ but also is some sort of free performance uplift/cheatery - because Wattage is only calculated in a 1h time base.
Soo given rounding and ramp time, short-term wattage limiter may not be such of a bad idea
~ while long term PL1 powerlimiter, should rather be a powersupply focused limiter.
Thermal throttle then is what bridges the (perf *) gap , as long as silicon was designed with such in mind.
* because powerlimiters are usually emergency throttles and do cause bad performance or even stutter scenarios.
~ same as TJMAX throttles ~ hence we have several types of thermal limiters too.
A ramp-time x hold-time topic.

But all of this is thrown out of the window with the specifications or so to say "extended extreme" (hah) targets for their XtremePowerProfile.
PL1 & PL2 match, and ICCMAX is just ICCMAX ~ PL4.

Given i'm nowhere near classified enough to talk about their substrate design and lack insight on their (Intel) manufacturing
I can not even imagine what would be the a good thermal/duration/loadtype - limiter for ICCMAX. When to extend it beyond~
Intel decides this is 400A for 14th gen & they don't publish specification on CPUs that will degrade in 1 year ~ so 400A it is :-)

I/we haven't seen a need for a powerlimiter anymore, when we have ICCMAX.
But i can be wrong and i do think that a healthy combination of PL2 + PL4 is better.
PL2 being ~27-30W above your Target Powerlimiter (PL1). Guessed-estimate.

A friend does recommend 320A (288W) for 13th gen and keeps the recommendation up for 14th gen.
I , kind of understand the recommendation reason ~ especially from a SystemIntegrator.
But the math doesn't add up to me, as that is ~348W PL2, this ICCMAX. This includes gathered knowledge of changed thermal-target with KS+14th gen.
Eh, everyone cooks differently and the only anchorpoint i can have is intel's target.
How good or maybe concerning, it sounds. Soo 400A it is. 🤭
- if I have a good cpu in terms of overall SP, do I still mess with the v/f curve at all since I don't think mine is leaky? is something like this worth doing on a good sp cpu or? and what am I aiming for in terms of looks for the curve?
The reason to mess with V/F is soo general headroom increases. // You can't control IMC upkeep voltage. But influence margins.
Given several clock's are connected and everything is loadbalanced ~ based on V/F curve
Given SA VID & UncoreVID play a critical role here (under the surface)

I would say ~ yes
A healthy mixture of linear dropping AC_LL (0.6 is a good starting point)
And a more substrate focused personal V/F.
Should be helpful to stay bellow the internal voltage limiters ~ which do track VID.
Some CPUs do come out of Lab with a sub 1.4 VID curve.
But this luxury doesnt work of every sample. // Especially as they target 105°c stability for SKUs clock-targets.
// Soo, many samples need the higher voltage, as they become leakier ~ yet no low-thermal foldoverpoint like it was mid 2015 at Skylake era.

Like above ~ while being slightly educated on now couple substrate behaviors (GloFo-14, GloFo-12, GloFo-12+, TSMC-7n)
I just had a recent Intel CPU for a very limited time.
~90 days.

A luxury time, vs the usually max-borrowed 30 days
But far too little, to dig deeper.
I'm sorry, for not being very helpful here.
- any idea if I should mess with SA PLL Frequency at all or leave auto? seen a couple people use it at 3200 but I can't find much good info on it at all
SA/SOC Freq matters for BLCK change
But , there was no need to mess with it.

Generally no PLL unless subzero or basically non existent margins
8600++
Its very suboptimal to touch PLL, vs just work with the voltage itself.
PLL limits max voltage range.
and what am I aiming for in terms of looks for the
Please read the posts from zebra_hun & tibcsi , over here.
Its about last 10 pages or 12.
I dont know how to summerize and compact it any further. Sorry

- if I were to use TVB with ICCMAX should I be going after a certain loadline to tune with or? current setup uses LLC6 but mostly because I haven't really tuned/messed with it since I had it working good last
Up to Board :)
One uses LLC 4, one stays at LLC3 that is default
Up to Board.

If you mean on the leaky/non-leaky topic.
mmm, complicated 🤭
because of the many variables. I wish i could answer it easier.

Try it out~
V/F tuning by itself is algorithmic.
At whatever LLC you run it, even if Vout will differ. The behavior will stay the same
LLC will change AC_LL minimums and targets. But more than that, barely.
It has thermal affectness too and noise , soo not bothering with it and trusting Boardengineer is rather the path to take
But outside of that SNR topic ~ its nearly linear.
Soo it will not be your worry when shaping V/F.

Now how substrate behaves
at which frequency point its more efficient
and what sort of droop amount it needs for this freq point, including factored AVX(2)/FMA offset
Eh , too many variables soo "its complicated, sorry".
Especially as my posts are already very big. Even with all linebreaks to easen topics.

Learn by trying :)
 
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@Veii
I set ICCMAX at 320A as you suggested and my clocks drop to 51/40/44 - 235w
Is this how its supposed to work or i do something wrong?
AC_Auto.png
 
Y-cruncher does hit PL4
HWInfo does show this:)

Yes~
Need to start undervolting V/F curve
To gain more clock and not hit PL4
I see, do I have to undervolt all V/F points?
Any recommendation how to start/test?
 
Do as before
WRRD_SG/DG is auto
So you don't have to do math every time you change CAS
Board has to be able to do the work for you

WTR tightening is helpful for perf.
tWR back to 24 ~ WRPRE/PDEN auto. Boards need to set them correctly
If you struggle, give 30 a shot. RTP still 12

Just go with your old foundation, not much has changed except Auto being more conservative.
Low level behavior change, shouldn't worry you.

Whatever you put tWR on. Its over WTRL as bare minimum. (because you miss a timing)
tWR in steps of 6 is good practice, but no requirement.

If you want to go fully failsafe and don't trust your dimms
BurstChop 8 = 8nCK
Anhang anzeigen 964591
This is the target.
In reality its lower with many "it depends"
High tWR eats a lot of perf.
Try it out and report back how big the loss is~
Games and other synthetics.

Hello, thanks for all the help.

I managed to raise Copy Speed.

tWR 24 works good with tWTR_L = 24 and tWTR_S = 4.

Nice improvement on performance.

240130032554 8200 CL36 tWTR BIOS Settings.jpg
 
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Hello,

Is there some way to try fix RTL's? Some reason all but 8400 works on default settings. Same exact settings on both only difference is frequency.
I've tried loosen primaries and setting auto for secondaries as show on pictures, but 8400 RTL's remain unmatched.

1.2 SA
1.4 TX
1.5 IMC
1.6 VDD
1.5 VDDQ

8400Mhz

Näyttökuva 2024-01-30 092217.png

8600Mhz

Näyttökuva 2024-01-30 094727.png
 
So, wollte mal Rückmeldung bezüglich des Colorful geben.
Also das BIOS ist wirklich übersichtlich. Es gibt keine Möglichkeit die CPU zu undervolten, lediglich P1 kann eingestellt werden.
Dazu gibt es keine Speicherplätze fürOC Profile! D.h. nach einem fehlgeschlagenen OC Versuch darf man alles schön neu eintippen. Das macht besonders bei meinen Hynix Green ohne xmp Profil richtig Spaß.
Auch werden gerne die Spannungsänderungen nicht übernommen.
Ich habe noch ein zweites Kit günstig erstanden und folgendes damit "geschafft":
IMG_20240130_113731.jpg

Leider habe ich vergessen die BIOS Einstellungen zu fotografieren:cautious:
Beitrag automatisch zusammengeführt:

Hier noch die Vielfalt im BIOS.
Verbesserungsvorschläge für die Spannungseinstellungen sind willkommen.
 

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@Veii

tyty appreciate all the info - didn't wanna quote the whole thing since its massive haha

right now i'm just using 400a ICCMAX otherwise everything else is stock/unlocked/auto including power limits/VR and no manual set voltages at all - so far in benchmarks like Cinebench it can hit like 280w but in gaming it's hardly ever at like 150-180 so i'm sure this is fine in the end, unlikely that games will use all of that up and even still 280 isn't really much above the 253 limit

however I did swap to LLC4 + spent a few hours tuning AC/DC LL, I use a weird OCTVB where all my cores can boost to 6200 and the 2 better cores with * next to them I have boost upto 6400, ring I have boost to 5200 - E cores stock at 4400

here is my curve with current setup no offsets or anything on the curve, based on what i've seen others look like i'm assuming this needs some work prob? also no clue if changing like LLC/AC-DCLL changes this or is this just static until I change v/f only?)
this is a SP106 14900k - 115p/88e/88-91mc - no SA bug
fdgdfdfgfdghj.png
 
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Silly y-cruncher is always complaining, that my coefficient is too large, and aborts.
 
I'm happy with this profile, it's much better than XMP.8th-)
I hope we can do better than that 🤭
1706585249480.png

Cut those away (put in 0). Its basically free performance without tradeoffs.
Because needed or not, they are still inserted.
_DD i like to use for their alternative usage.
But there is no different Rank at all. Neither logical rank * on single sided modules.

R2-R7 RTL to zero and those to zero.
You need to do both.


* Subchannels may be able to be seen as logical rank, up to how interleaving happens
But its not too different from subchannel interleaving.
_DR is not a subchannel based timing.
_DD may or may not have several usecases when it comes to channel layout. Its not only dual side ** focused.

** Especially because memory on 2nd channel has identical layd out gold fingers
If connectivity design (arch) to mem is run as 64bit channels, instead multiple 32bit
It can interact with it.
You still are at the margin of BurstChop as bare bare minimum ~ which remains 8

But because UDIMM can never be real dualrank , rather dual row + dual rank
It can never process more than one row at the same time per channel per rank
It can only do simultaneous operations, if top and bottom Row of ICs are connected at the same time
@Veii

tyty appreciate all the info - didn't wanna quote the whole thing since its massive haha

right now i'm just using 400a ICCMAX otherwise everything else is stock/unlocked/auto including power limits/VR and no manual set voltages at all - so far in benchmarks like Cinebench it can hit like 280w but in gaming it's hardly ever at like 150-180 so i'm sure this is fine in the end, unlikely that games will use all of that up and even still 280 isn't really much above the 253 limit

however I did swap to LLC4 + spent a few hours tuning AC/DC LL, I use a weird OCTVB where all my cores can boost to 6200 and the 2 better cores with * next to them I have boost upto 6400, ring I have boost to 5200 - E cores stock at 4400

here is my curve with current setup no offsets or anything on the curve, based on what i've seen others look like i'm assuming this needs some work prob? also no clue if changing like LLC/AC-DCLL changes this or is this just static until I change v/f only?)
this is a SP106 14900k - 115p/88e/88-91mc - no SA bug
Anhang anzeigen 965358
This does voltage correct for some reason
Its really bad.

Whatever you tuned with AC_LL, please revert and resubmit the curve.
Any voltage point onwards that is loewr than the previous voltage point, is ignored and skipped
Look at how many spikes exist before the next voltage point

It is not capable to boost high on one frequency point and drop voltage on the next.
It will ignore this point completely.

Sorry for the harsh answer.
Beitrag automatisch zusammengeführt:

I see, do I have to undervolt all V/F points?
Any recommendation how to start/test?
Last 12-15 pages.
Everything is written out.
The talk with zebra_hun and tibcsi
 
This does voltage correct for some reason
Its really bad.

Whatever you tuned with AC_LL, please revert and resubmit the curve.
Any voltage point onwards that is loewr than the previous voltage point, is ignored and skipped
Look at how many spikes exist before the next voltage point

It is not capable to boost high on one frequency point and drop voltage on the next.
It will ignore this point completely.

Sorry for the harsh answer.
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all good :) not harsh at all idk too much about this stuff outside of most recent stuff i've read here really and a few other things from other random forums/posts - otherwise yeah this was with LLC4 even trying to change the ACLL back or around it resulted in this:
dfgu5fgh.png


but here is with LLC6 that i had tuned before:

zsfddfd.png
 
all good :) not harsh at all idk too much about this stuff outside of most recent stuff i've read here really and a few other things from other random forums/posts - otherwise yeah this was with LLC4 even trying to change the ACLL back or around it resulted in this:
Anhang anzeigen 965380

but here is with LLC6 that i had tuned before:

Anhang anzeigen 965383
P11 +25mV
P10 -18mV

Auto LLC
Please resubmit the screenshot-change
AC_LL at .65 for now

What was your CPU V/F again ?
EDIT:
I use a weird OCTVB where all my cores can boost to 6200 and the 2 better cores with * next to them I have boost upto 6400, ring I have boost to 5200 - E cores stock at 4400
Do you actually try to run 6.4GHz TVB or does the tool bug out ?
Nvm.
Maybe dont do that, till you havent verified mem stability/limits neither render perf
Clock means nothing.
 
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P11 +25mV
P10 -18mV

Auto LLC
Please resubmit the screenshot-change
AC_LL at .65 for now

What was your CPU V/F again ?
EDIT:

Do you actually try to run 6.4GHz TVB or does the tool bug out ?
Nvm.
Maybe dont do that, till you havent verified mem stability/limits neither render perf
Clock means nothing.
Ok so did some quick tests before I gotta leave again, messed with some v/f points - think I got the hang of it for the most part (hopefully), though I did remove the 6400 for now cause I figured it would be easier to tune/learn the v/f stuff with just normal tvb for now, maybe i'll go back for the 6400 eventually but really wasn't needed

here is my cpus v/f and new updated curve after messing with some stuff
sdffsd.png

56ygdfd.png
 
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I hope we can do better than that 🤭
Anhang anzeigen 965098
Cut those away (put in 0). Its basically free performance without tradeoffs.
Because needed or not, they are still inserted.
_DD i like to use for their alternative usage.
But there is no different Rank at all. Neither logical rank * on single sided modules.

R2-R7 RTL to zero and those to zero.
You need to do both.


* Subchannels may be able to be seen as logical rank, up to how interleaving happens
But its not too different from subchannel interleaving.
_DR is not a subchannel based timing.
_DD may or may not have several usecases when it comes to channel layout. It's not only dual side ** focused.

Wow, look at that read, write, and copy,.. with just cutting those away (put in 0),.. that's amazing.

Edit: Both Channels, thanks CarSalesman.

Screenshot 2024-01-30 220753 8200C36 RTL-0 both channels.png Screenshot 2024-01-30 215930 8200C36 RTL-0.png Screenshot 2024-01-30 152437 write.png Screenshot 2024-01-30 152602 copy.png Screenshot 2024-01-30 153906 Latency.png
 
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Jungs, hab mal ne Frage. Mir ist aufgefallen, dass bei vielen quad steht bei Channel. Bei einigen single. Natürlich auf dem apex. Wieso das? Und was sind die Unterschiede zb quad 8400 oder single?
 
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Guten Morgen,
Ich bin am verzweifeln 💀Komme vom Gigabyte Z790 Elite AX Rev. 1.0.
Dort liefen 7400c34 stabil wie ein Fels in der Brandung. Nun hab ich das Z690 Aqua Oc fast geschenkt bekommen und bekomme die 7000 nicht einmal gebootet. Die Spannungen Vdd_Cpu = vdd2 geht nicht höher als 1.4 volt und imc_cpu geht auch nicht höher als 1.4 volt. Habe mit asrock leider auch keine Erfahrung, ist hier jmd der mir weiterhelfen könnte? Das Board soll ja angeblich 8k+ machen und meine CPU geht vom imc safe 7400.
 
nö, schon asrock selbst sagt up to 7000. 4 dimm z690 board halt. 6400 sind wohl realistischer.
Es ist das OC.. 2 dimm board. 12 layer Platine und wie gesagt kursieren Screenshots von 8000+ im Netz.
 
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