PCR(PCI Configration Registers) Editor / WPCREDIT for WIN32
Copyright (c) 2000 H.Oda!
[COMMENT]=Author H.Oda!
[MODEL]=K7S5A (SiS735)
[VID]=1039:SiS
[DID]=0735:Host to PCI Bridge
(00)=Vendor Identification
(01)=Vendor Identification
(02)=Device Identification
(03)=Device Identification
[04:7]=(RESERVED)
[04:6]=(RESERVED)
[04:5]=(RESERVED)
[04:4]=(RESERVED)
[04:3]=(RESERVED)
[04:2]=(RESERVED)
[04:1]=(RESERVED)
[04:0]=(RESERVED)
[05:7]=(RESERVED)
[05:6]=(RESERVED)
[05:5]=(RESERVED)
[05:4]=(RESERVED)
[05:3]=(RESERVED)
[05:2]=Bus Master - RO - Default 1 0=can disable 1=cannot
[05:1]=PCI Master Memory Space Access 0=disable 1=enable
[05:0]=I/O Space - RO - Def=1 Host Bridge I/O only at 0CF8h,0CFCh
[06:7]=(RESERVED) RO
[06:6]=(RESERVED) RO
[06:5]=Received Master Abort - WC
[06:4]=Received Target Abort - WC
[06:3]=(RESERVED)
[06:2]=DEVSEL# Timing DEVT
[06:1]=(Same as bit2)
[06:0]=(RESERVED) RO
[07:7]=(RESERVED) RO
[07:6]=(RESERVED) RO
[07:5]=(RESERVED) RO
[07:4]=CAP_LIST - RO - 0=No Cap. listed 1=Cap. listed
[07:3]=(RESERVED) RO
[07:2]=(RESERVED) RO
[07:1]=(RESERVED) RO
[07:0]=(RESERVED) RO
(08)=Revision ID RO
(09)=Programming Interface RO
(0A)=Sub Class Code RO
(0B)=Base Class Code RO
(0C)=Cache Line Size RO
(0D)=Host/PCI Bridge Latency PCI Clocks
(0E)=Header Type RO
(0F)=Built-in Self Test RO
[10:7]=Graphics Window Base Address
[10:6]=(Same as bit7)
[10:5]=(Same as bit7)
[10:4]=(Same as bit7)
[10:3]=(Same as bit7)
[10:2]=(Same as bit7)
[10:1]=(Same as bit7)
[10:0]=(Same as bit7)
[11:7]=(Same as bit7, 10h)
[11:6]=(Same as bit7, 10h)
[11:5]=(RESERVED) RO
[11:4]=(RESERVED) RO
[11:3]=(RESERVED) RO
[11:2]=(RESERVED) RO
[11:1]=(RESERVED) RO
[11:0]=(RESERVED) RO
[12:7]=(RESERVED) RO
[12:6]=(RESERVED) RO
[12:5]=(RESERVED) RO
[12:4]=(RESERVED) RO
[12:3]=(RESERVED) RO
[12:2]=(RESERVED) RO
[12:1]=(RESERVED) RO
[12:0]=(RESERVED) RO
[13:7]=(RESERVED) RO
[13:6]=(RESERVED) RO
[13:5]=(RESERVED) RO
[13:4]=(RESERVED) RO
[13:3]=(RESERVED) RO
[13:2]=(RESERVED) RO
[13:1]=(RESERVED) RO
[13:0]=(RESERVED) RO
(2C)=Upper byte, Subsystem ID R/WO
(2D)=Lower byte, Subsystem ID R/WO
(2E)=Upper byte, Subsystem Vendor ID R/WO
(2F)=Lower byte, Subsystem Vendor ID R/WO
(34)=AGP standard registers block start addr RO
[50:7]=CPU PCI/AGP post write 0=enable 1=disable
[50:6]=PCI/AGP write pre-order 0=disable* 1=enable
[50:5]=Monochrome Display 0=None 1=Present
[50:4]=CPU/ViD Mem Access Prio 00=Rotate 01=AGP Priority
[50:3]=(Same as bit4)
[50:2]=Memory Request Latency 0=Normal 1=Fast
[50:1]=BIU/PCI Memory Pipeline 0=Disable 1=Enable
[50:0]=Mask Read Error 0=Unmask 1=Mask
[51:7]=CPU/Memory Write Pipeline 0=disable 1=enable
[51:6]=Pipeline Speed 0=normal 1=fast
[51:5]=CPU/Memory Read Pipeline 0=disable 1=enable
[51:4]=Async Mem Read Latency 0=CPU Clock 1=Mem clock
[51:3]=CPU/PCI to AGP Arbitration Rate X0=1 Trans 01=8 Trans
[51:2]=(same as bit3)
[51:1]=Read Arbitration, PCI33&66 0=command 1=transaction
[51:0]=Write Arbitration, PCI33&66 0=command 1=transaction
[52:7]=(Reserved)
[52:6]=SysDC Probe Command Counter
[52:5]=(same as bit6)
[52:4]=(same as bit6)
[52:3]=(Reserved)
[52:2]=SysDC Read Commmand Counter
[52:1]=(same as bit2)
[52:0]=(same as bit2)
[53:7]=DDR Async Read Latency 0=normal 1=fast
[53:6]=Max PCI/AGP cycles to sys mem
[53:5]=(same as bit6)
[53:4]=(same as bit6)
[53:3]=(Reserved)
[53:2]=SysDC Write Command Counter
[53:1]=(same as bit2)
[53:0]=(same as bit2)
(54)=Data In Control Register
(55)=(same as 54)
(56)=(same as 54)
(57)=(same as 54)
[58:7]=SDR/DDR tRAS 00=6T 01=7T 10=5T 11=4T
[58:6]=(same as bit7)
[58:5]=SDR/DDR tRP 00=3T 01=2T 10=4T 11=RESERVED
[58:4]=(same as bit5)
[58:3]=SDR/DDDR tRCD 00=3T 01=2T 10=4T 11=RESERVED
[58:2]=(same as bit3)
[58:1]=SDR/DDR tRC 0=tRAS+tRP 1=tRAS+tRP+1T
[58:0]=SDR/DDR tRRD 0=2T 1=3T
[59:7]=(Reserved)
[59:6]=SDR/DDR tWR 0=2T 1=1T
[59:5]=SDR/DDR CL DDR: 00=Reserved 01=2T 10=2.5T 11=3T
[59:4]=SDR: 00=Reserved 01=2T 10=Reserved 11=3T
[59:3]=SDR/DDR R/W Turn-around time 00=Safe 01=Normal
[59:2]=10=Fast 11=Ultra
[59:1]=SDR/DDR Read Latency 00=Safe 01=Normal
[59:0]=10=Fast 11=Ultra
[5A:7]=(Reserved)
[5A:6]=(Reserved)
[5A:5]=Mem R/W Lead-off 0=1 clock behind MA 1=concurrent
[5A:4]=Mem Backgrd Access 0=1 clock behind MA 1=concurrent
[5A:3]=CPU Access Latency 0=Normal 1=Fast
[5A:2]=Mem Back/Back Write Latency 0=Slow 1=Normal
[5A:1]=Mem Sizing Read Align 0=Normal 1=Invert
[5A:0]=SDR Read Latency 0=Safe 1=Fast
[5B:7]=FG & BG Cmd out of order Ctl 0=Enable async 1=disable
[5B:6]=Background Queue Depth 0=2 1=1
[5B:5]=Foreground Queue Depth 00=3 01=2
[5B:4]=10=1 11=Reserved
[5B:3]=(Reserved)
[5B:2]=SDR Page Control 0=Multi 1=Single Page Access
[5B:1]=Read Combine Function 0=enable 1=disable
[5B:0]=Write Combine Function 0=enable 1=disable
[5C:7]=(Reserved)
[5C:6]=SDR/DDR Init Command Sequence
[5C:5]=000=NOP 001=PALL 010=MRS 011=REF 100=EMRS-Normal
[5C:4]=101=EMRS-Weak 110=DLL-Reset 111=RS DLL Disable
[5C:3]=Issue SDR/DDR Init Command 0=disable 1=enable
[5C:2]=DDR Read Stage Dynamic Reset 0=enable 1=disable
[5C:1]=DDR MD/DQS Input Enable 0=disable 1=enable
[5C:0]=SDR MD Output Enable 0=disable 1=enable
[5D:7]=DRAM Refresh Queue Depth
[5D:6]=00=0 01=4 10=8 11=12
[5D:5]=DRAM Refresh Period Control 00=15.6us
[5D:4]=01=7.8us 10=3.9us 11=Reserved
[5D:3]=DRAM Stagger Bank Rfrsh 0=Simul 1=Staggered 1 clock
[5D:2]=CBR refresh Ctr Clock 0=100MHz 1=133MHz
[5D:1]=DRAM Refresh Test Mode 0=Normal 1=Test
[5D:0]=Refresh Cycle Enable 0=disable 1=enable
[5E:7]=(Reserved)
[5E:6]=(Reserved)
[5E:5]=(Reserved)
[5E:4]=(Reserved)
[5E:3]=(Reserved)
[5E:2]=(Reserved)
[5E:1]=Ahead Refresh Clocks 0=10T 1=40T
[5E:0]=Ahead Refresh Enable 0=disable 1=enable
[60:7]=(Reserved) (DIMM0)
[60:6]=DRAM Mode Sel 0=SDR 1=DDR
[60:5]=DRAM Config 0=Single Side 1=Double Side
[60:4]=(Reserved)
[60:3]=DRAM Size 0000=1x11x8 0001=1x13x8 0010=2x12x8 0011=2x13x8
[60:2]=0100=1x11x9 0101=1x13x9 0110=2x12x9 0111=2x13x9
[60:1]=1000=2x12x10 1001=1x13x10 1010=2x12x10 1011=2X13X10
[60:0]=1100=2X11X8 1101=2X13X12 1110=2x12x11 1111=2x13x11
[61:7]=(Reserved) (DIMM1)
[61:6]=DRAM Mode Sel 0=SDR 1=DDR
[61:5]=DRAM Config 0=Single Side 1=Double Side
[61:4]=(Reserved)
[61:3]=DRAM Size 0000=1x11x8 0001=1x13x8 0010=2x12x8 0011=2x13x8
[61:2]=0100=1x11x9 0101=1x13x9 0110=2x12x9 0111=2x13x9
[61:1]=1000=2x12x10 1001=1x13x10 1010=2x12x10 1011=2X13X10
[61:0]=1100=2X11X8 1101=2X13X12 1110=2x12x11 1111=2x13x11
[62:7]=(Reserved) (DIMM2)
[62:6]=DRAM Mode Sel 0=SDR 1=DDR
[62:5]=DRAM Config 0=Single Side 1=Double Side
[62:4]=(Reserved)
[62:3]=DRAM Size 0000=1x11x8 0001=1x13x8 0010=2x12x8 0011=2x13x8
[62:2]=0100=1x11x9 0101=1x13x9 0110=2x12x9 0111=2x13x9
[62:1]=1000=2x12x10 1001=1x13x10 1010=2x12x10 1011=2X13X10
[62:0]=1100=2X11X8 1101=2X13X12 1110=2x12x11 1111=2x13x11
[63:7]=(Reserved) (DIMM3)
[63:6]=DRAM Mode Sel 0=SDR 1=DDR
[63:5]=DRAM Config 0=Single Side 1=Double Side
[63:4]=(Reserved)
[63:3]=DRAM Size 0000=1x11x8 0001=1x13x8 0010=2x12x8 0011=2x13x8
[63:2]=0100=1x11x9 0101=1x13x9 0110=2x12x9 0111=2x13x9
[63:1]=1000=2x12x10 1001=1x13x10 1010=2x12x10 1011=2X13X10
[63:0]=1100=2X11X8 1101=2X13X12 1110=2x12x11 1111=2x13x11
[64:7]=(Reserved)
[64:6]=(Reserved)
[64:5]=(Reserved)
[64:4]=(Reserved)
[64:3]=DRAM DIMM3 Status 0=Absent 1=Installed
[64:2]=DRAM DIMM2 Status 0=Absent 1=Installed
[64:1]=DRAM DIMM1 Status 0=Absent 1=Installed
[64:0]=DRAM DIMM0 Status 0=Absent 1=Installed
[68:7]=A[15:8], ACPI I/O Base Address (Word spanning 69-68h)
[68:6]=(same as bit7)
[68:5]=(same as bit7)
[68:4]=(same as bit7)
[68:3]=(same as bit7)
[68:2]=(same as bit7)
[68:1]=(same as bit7)
[68:0]=(same as bit7)
[69:7]=(Reserved)
[69:6]=(Reserved)
[69:5]=(Reserved)
[69:4]=(Reserved)
[69:3]=(Reserved)
[69:2]=(Reserved)
[69:1]=(Reserved)
[69:0]=ACPI I/O Base Address 15:8 0=Invalid 1=Valid
[6A:7]=ACPI C3 Self-Refresh 0=disable 1=enable
[6A:6]=ACPI C2 Self-Refresh 0=disable 1=enable
[6A:5]=ACPI C1 Self-Refresh 0=disable 1=enable
[6A:4]=ACPI S3 Disconnect Enable 0=disable 1=enable
[6A:3]=ACPI S1 Disconnect Enable 0=disable 1=enable
[6A:2]=ACPI C3 Disconnect Enable 0=disable 1=enable
[6A:1]=ACPI C2 Disconnect Enable 0=disable 1=enable
[6A:0]=ACPI C1 Disconnect Enable 0=disable 1=enable
[70:7]=PCI Master Read Shadow Ram 0=PCI 1=Shadow Ram
[70:6]=(Reserved)
[70:5]=(Reserved)
[70:4]=Read Shadow Region F0000h-FFFFFh 0=PCI 1=Shadow Ram
[70:3]=Read Shadow Region EC000h-EFFFFh 0=PCI 1=Shadow Ram
[70:2]=Read Shadow Region E8000h-EBFFFh 0=PCI 1=Shadow Ram
[70:1]=Read Shadow Region E4000h-E7FFFh 0=PCI 1=Shadow Ram
[70:0]=Read Shadow Region E0000h-E3FFFh 0=PCI 1=Shadow Ram
[71:7]=Read Shadow Region DC000h-DFFFFh 0=PCI 1=Shadow Ram
[71:6]=Read Shadow Region D8000h-DBFFFh 0=PCI 1=Shadow Ram
[71:5]=Read Shadow Region D4000h-D7FFFh 0=PCI 1=Shadow Ram
[71:4]=Read Shadow Region D0000h-D3FFFh 0=PCI 1=Shadow Ram
[71:3]=Read Shadow Region CC000h-CFFFFh 0=PCI 1=Shadow Ram
[71:2]=Read Shadow Region C8000h-CBFFFh 0=PCI 1=Shadow Ram
[71:1]=Read Shadow Region C4000h-C7FFFh 0=PCI 1=Shadow Ram
[71:0]=Read Shadow Region C0000h-C3FFFh 0=PCI 1=Shadow Ram
[72:7]=PCI Master Write Shadow Ram 0=PCI 1=Shadow Ram
[72:6]=(Reserved)
[72:5]=(Reserved)
[72:4]=Write Shadow Region F0000h-FFFFFh 0=PCI 1=Shadow Ram
[72:3]=Write Shadow Region EC000h-EFFFFh 0=PCI 1=Shadow Ram
[72:2]=Write Shadow Region E8000h-EBFFFh 0=PCI 1=Shadow Ram
[72:1]=Write Shadow Region E4000h-E7FFFh 0=PCI 1=Shadow Ram
[72:0]=Write Shadow Region E0000h-E3FFFh 0=PCI 1=Shadow Ram
[72:7]=Write Shadow Region DC000h-DFFFFh 0=PCI 1=Shadow Ram
[72:6]=Write Shadow Region D8000h-DBFFFh 0=PCI 1=Shadow Ram
[72:5]=Write Shadow Region D4000h-D7FFFh 0=PCI 1=Shadow Ram
[72:4]=Write Shadow Region D0000h-D3FFFh 0=PCI 1=Shadow Ram
[72:3]=Write Shadow Region CC000h-CFFFFh 0=PCI 1=Shadow Ram
[72:2]=Write Shadow Region C8000h-CBFFFh 0=PCI 1=Shadow Ram
[72:1]=Write Shadow Region C4000h-C7FFFh 0=PCI 1=Shadow Ram
[72:0]=Write Shadow Region C0000h-C3FFFh 0=PCI 1=Shadow Ram
[77:7]=(Reserved)
[77:6]=(Reserved)
[77:5]=(Reserved)
[77:4]=(Reserved)
[77:3]=(Reserved)
[77:2]=PCI-Hole Area I 0=disable 1=enable
[77:1]=(Reserved)
[77:0]=PCI-Hole Area II 0=disable 1=enable
[78:7]=PCI-Hole I Size 000=64KB 001=128KB
[78:6]=010=256KB 011=512KB 100=1MB
[78:5]=101=2MB 110=4MB 111=8MB
[78:4]=Base Address, PCI-HOLE I (13 Bits)
[78:3]=(same as bit4)
[78:2]=(same as bit4)
[78:1]=(same as bit4)
[78:0]=(same as bit4)
[79:7]=(same as 78H bit4)
[79:6]=(same as 78H bit4)
[79:5]=(same as 78H bit4)
[79:4]=(same as 78H bit4)
[79:3]=(same as 78H bit4)
[79:2]=(same as 78H bit4)
[79:1]=(same as 78H bit4)
[79:0]=(same as 78H bit4)
[7A:7]=PCI-Hole II Size 000=64KB 001=128KB
[7A:6]=010=256KB 011=512KB 100=1MB
[7A:5]=101=2MB 110=4MB 111=8MB
[7A:4]=Base Address, PCI-HOLE II (13 Bits)
[7A:3]=(same as bit4)
[7A:2]=(same as bit4)
[7A:1]=(same as bit4)
[7A:0]=(same as bit4)
[7B:7]=(same as 7AH bit4)
[7B:6]=(same as 7AH bit4)
[7B:5]=(same as 7AH bit4)
[7B:4]=(same as 7AH bit4)
[7B:3]=(same as 7AH bit4)
[7B:2]=(same as 7AH bit4)
[7B:1]=(same as 7AH bit4)
[7B:0]=(same as 7AH bit4)
[80:7]=(Reserved)
[80:6]=(Reserved)
[80:5]=(Reserved)
[80:4]=(Reserved)
[80:3]=CPU-to-PCI33 Front-end Retry 0000=Once 0010=3 Times*
[80:2]=(same as bit3)
[80:1]=(same as bit3)
[80:0]=(same as bit3)
[81:7]=Host Bridge Burst Control 0=enable 1=disable
[81:6]=Post-write PCI combine 0=enable 1=disable
[81:5]=Config-to-Special Conversion 0=enable 1=disable
[81:4]=Target Abort 0=Immediate 1=Try one more time
[81:3]=Dummy CPU-to-PCI Cycles Filter 0=disable 1=enable
[81:2]=(Reserved)
[81:1]=(Reserved)
[81:0]=(Reserved)
[82:7]=(Reserved)
[82:6]=(Reserved)
[82:5]=CPU to PCI Access Latency 0=Normal 1=Fast*
[82:4]=Back-to-Back CPU/PCI Performance 0=Normal 1=Fast*
[82:3]=(Reserved)
[82:2]=(Reserved)
[82:1]=(Reserved)
[82:0]=(Reserved)
[83:7]=(Reserved)
[83:6]=(Reserved)
[83:5]=(Reserved)
[83:4]=(Reserved)
[83:3]=PCI Parking Grant 0=Park on Host Bridge 1=Park on PCI Master
[83:2]=Host Bridge & PCI Master Priority (Larger
[83:1]=Value==Lower Host Bridge Priority
[83:0]=(same as bit2 and bit1)
[84:7]=Write Latency Reserved Buffer Size (4 bits)
[84:6]=(same as bit7)
[84:5]=(same as bit7)
[84:4]=(same as bit7)
[84:3]=Write Latency Control Test 0=disable* 1=enable
[84:2]=Abort Disconnected Delayed Transaction 0=disable* 1=enable
[84:1]=PCI Same Memory Read 0=disable* 1=enable, only same mem
[84:0]=PCI Memory Read Prefetch 0=disable 1=enable*
[85:7]=PCI Discard Timer, Delayed Trans. (in PCI Clocks, 16 bits)
[85:6]=(same as bit7)
[85:5]=(same as bit7)
[85:4]=(same as bit7)
[85:3]=(same as bit7)
[85:2]=(same as bit7)
[85:1]=(same as bit7)
[85:0]=(same as bit7)
[86:7]=(same as 85H bit7)
[86:6]=(same as 85H bit7)
[86:5]=(same as 85H bit7)
[86:4]=(same as 85H bit7)
[86:3]=(same as 85H bit7)
[86:2]=(same as 85H bit7)
[86:1]=(same as 85H bit7)
[86:0]=(same as 85H bit7)
[87:7]=(Reserved)
[87:6]=(Reserved)
[87:5]=(Reserved)
[87:4]=(Reserved)
[87:3]=(Reserved)
[87:2]=(Reserved)
[87:1]=(Reserved)
[87:0]=Write Promotion Control 0=disable 1=enable*
[88:7]=EDB Posted-Write Grant Timer (in PCI Clocks)
[88:6]=(same as bit7)
[88:5]=(same as bit7)
[88:4]=(same as bit7)
[88:3]=(same as bit7)
[88:2]=(same as bit7)
[88:1]=(same as bit7)
[88:0]=(same as bit7)
[89:7]=EDB Write Channel 0=Both Channels 1=One Channel
[89:6]=Disable EDB Write Chan. Select 0=disable Chan 0 1=Chan 1
[89:5]=EDB Read Channel 0=Both Channels 1=One Channel
[89:4]=Disable EDB Read Chan. Select 0=disable Chan 0 1=Chan 1
[89:3]=EDB Read Partition Boundary 0=4QW 1=8 QW
[89:2]=R88h Grant Timer EDB Disconnect 0=disable 1=enable*
[89:1]=EDB Write Transaction Test 0=disable 1=enable
[89:0]=(Reserved)
[8A:7]=EDB Write Chan 0 Cmd FIFO depth 0=8 levels 1=4 levels
[8A:6]=EDB Write Chan 1 Cmd FIFO depth 0=8 levels 1=4 levels
[8A:5]=EDB Write Chan 0 Data FIFO depth 0=16 QW 1=8 QW
[8A:4]=EDB Write Chan 1 Data FIFO depth 0=16 QW 1=8 QW
[8A:3]=EDB Read Chan 0 Cmd FIFO depth 0=8 levels 1=5 levels
[8A:2]=EDB Read Chan 1 Cmd FIFO depth 0=8 levels 1=5 levels
[8A:1]=(Reserved)
[8A:0]=(Reserved)
[8B:7]=EDB Peer-to-Peer Cycle Counter (8 bits)
[8B:6]=00h=0 transactions
[8B:5]=04h=4 transactions*
[8B:4]=(same as bit7, bit6, bit5)
[8B:3]=(same as bit7, bit6, bit5)
[8B:2]=(same as bit7, bit6, bit5)
[8B:1]=(same as bit7, bit6, bit5)
[8B:0]=(same as bit7, bit6, bit5)
[90:7]=GART Base Address (20 bits)
[90:6]=(same as bit7)
[90:5]=(same as bit7)
[90:4]=(same as bit7)
[90:3]=(same as bit7)
[90:2]=(same as bit7)
[90:1]=(same as bit7)
[90:0]=(same as bit7)
[91:7]=(same as 90H bit7)
[91:6]=(same as 90H bit7)
[91:5]=(same as 90H bit7)
[91:4]=(same as 90H bit7)
[91:3]=(same as 90H bit7)
[91:2]=(same as 90H bit7)
[91:1]=(same as 90H bit7)
[91:0]=(same as 90H bit7)
[92:7]=(same as 90H bit7)
[92:6]=(same as 90H bit7)
[92:5]=(same as 90H bit7)
[92:4]=(same as 90H bit7)
[92:3]=(Reserved)
[92:2]=(Reserved)
[92:1]=(Reserved)
[92:0]=(Reserved)
[93:7]=(Reserved)
[93:6]=(Reserved)
[93:5]=(Reserved)
[93:4]=(Reserved)
[93:3]=(Reserved)
[93:2]=(Reserved)
[93:1]=(Reserved)
[93:0]=(Reserved)
[94:7]=(Reserved)
[94:6]=Graphic Window Size 000=4M 001=8M
[94:5]=010=16M 011=32M 100=64M
[94:4]=101=128M 110=256M 111=Reserved
[94:3]=(Reserved)
[94:2]=(Reserved)
[94:1]=Graphic Window Base Address 0=invalid addr 1=valid
[94:0]=GART Remap Base Address (90h) 0=invalid addr 1=valid
[95:7]=(Reserved)
[95:6]=(Reserved)
[95:5]=(Reserved)
[95:4]=(Reserved)
[95:3]=(Reserved)
[95:2]=(Reserved)
[95:1]=GART-Write Blocks AGP Request 0=AGP BlocKed 1=AGP Grant
[95:0]=GW-Write Blocks AGP Request 0=AGP BlocKed 1=AGP Grant
[97:7]=(Reserved)
[97:6]=(Reserved)
[97:5]=(Reserved)
[97:4]=(Reserved)
[97:3]=(Reserved)
[97:2]=GART-Write Stalled Page Cache Block 0=Block 1=Grant
[97:1]=(Reserved)
[97:0]=GART Page Table Cache 0=disable 1=enable
[98:7]=(Reserved)
[98:6]=(Reserved)
[98:5]=(Reserved)
[98:4]=(Reserved)
[98:3]=(Reserved)
[98:2]=(Reserved)
[98:1]=Invalidate Page Table Cache 1=Invalidate, auto cleared
[98:0]=(Reserved)
[99:7]=(Reserved)
[99:6]=SDRCLK Delay Control, Delays in ns are 000=0.0 001=0.5
[99:5]=010=1.0 011=1.5 100=2.0
[99:4]=101=2.5 110=3.0 111=3.5
[99:3]=(Reserved)
[99:2]=(Reserved)
[99:1]=(Reserved)
[99:0]=DDR IO Input Mode 0=Differential Mode 1=Bypass Mode
[9A:7]=Strobe Signal Delay Offset (ns) 000=-0.6 001=-0.4
[9A:6]=010=-0.2 011=0.0 100=+0.2
[9A:5]=101=+0.4 110=+0.6 111=+0.8
[9A:4]=Strobe Signal Delay 0=disable 1=enable
[9A:3]=Strobe Signal Delay, Initial value (ns) 0000=0.8
[9A:2]=0001=1.0 0010=1.2 0011=1.4 0100=1.6 0101=1.8 0110=2.0
[9A:1]=0111=2.2 1000=2.4 1001=2.6 1010=2.8 1011=3.0 1100=3.2
[9A:0]=1101=3.4 1110=3.6 1111=3.8
[9B:7]=(Reserved)
[9B:6]=AGP TCLK Delay (ns) 000=-0.5 001=0.0
[9B:5]=010=+0.5 011=+1.0 100=+1.5
[9B:4]=101=+2.0 110=+2.5 111=+3.0
[9B:3]=(Reserved)
[9B:2]=(Reserved)
[9B:1]=(Reserved)
[9B:0]=CPUCLK/SDCLK Synchronous Control 1=Sync 2=Async
[9C:7]=(Reserved)
[9C:6]=(Reserved)
[9C:5]=Signal Hold Time (ns) 00=+0.5
[9C:4]=01=+1.0 10=+1.5 11=+2.0
[9C:3]=(Reserved)
[9C:2]=(Reserved)
[9C:1]=MD Signal Hold Time 00=+0.5
[9C:0]=01=+1.0 10=+1.5 11=+2.0
[9D:7]=(Reserved)
[9D:6]=(Reserved)
[9D:5]=DQM Signal Hold Time (ns) 00=+0.5
[9D:4]=01=+1.0 10=+1.5 11=+2.0
[9D:3]=(Reserved)
[9D:2]=(Reserved)
[9D:1]=MA Signal Hold Time (ns) 00=+0.5
[9D:0]=01=+1.0 10=+1.5 11=+2.0
[9E:7]=(Reserved)
[9E:6]=(Reserved)
[9E:5]=CS Signal Hold Time (ns) 00=+0.5
[9E:4]=01=+1.0 10=+1.5 11=+2.0
[9E:3]=(Reserved)
[9E:2]=(Reserved)
[9E:1]=DQS/CSB Signal Hold Time (ns) 00=+0.5
[9E:0]=01=+1.0 10=+1.5 11=+2.0
[9F:7]=FWSDCLKO Timing Control 0=Early Clock 1=No Early Clock
[9F:6]=(Reserved)
[9F:5]=CKE Setup Time 00=Normal
[9F:4]=01=Early 0.5T 10=Early 1T 11=Reserved
[9F:3]=CKE Hold Time (ns) 0000=+0.5 0001=+1.0
[9F:2]=0010=+1.5 0011=+2.0 0100=+2.5 0101=+3.0 0110=+3.5
[9F:1]=0111=+4.0 1000=+4.5 1001=+5.0 1010=+5.5 1011=+6.0
[9F:0]=1100=+6.5 1101=+7.0 1110=+7.5 1111=+8.0
[A0:7]=Output DQS Signal Delay (ns) 00=+0.0
[A0:6]=01=+0.2 10=+0.4 11=+0.6
[A0:5]=Output MD Signal Delay (ns) 00=+0.0
[A0:4]=01=+0.2 10=+0.4 11=+0.6
[A0:3]=MD[63:0] Pre-Driver Slew 0=Normal 1=Fast
[A0:2]=MD[63:0] Driving 00=0.5X 001=1.0X
[A0:1]=010=1.5X 011=2.0X 100=2.5X
[A0:0]=101=3.0X 110=3.5X 111=4.0X
[A1:7]=DQM[7:0] Pre-driver Slew 0=Normal 1=Fast
[A1:6]=DQM[7:0] Driver Rating 000=0.5x 001=1.0X
[A1:5]=010=1.5x 011=2.0x 100=2.5x
[A1:4]=101=3.0x 110=3.5x 111=4.0x
[A1:3]=SRAS#/SCAS#/WE#/MA[14:0] Pre-driver Slew 0=Normal 1=Fast
[A1:2]=(Reserved)
[A1:1]=SRAS#/SCAS#/WE#/MA[14:0] Driver Rating 00=1X
[A1:0]=01=2X 10=3X 11=4X
[A2:7]=CS[5:0]# Pre-Driver Slew 0=Normal 1=Fast
[A2:6]=(Reserved)
[A2:5]=CS[5:0]# Driving 00=0.5X
[A2:4]=01=1.0x 10=1.5x 11=2.0x
[A2:3]=DQS[7:0]/CSB[7:0]# Pre-driver Slew 0=Normal 1=Fast
[A2:2]=DQS[7:0]/CSB[7:0]# Driving 000=0.5X 001=1.0X
[A2:1]=010=1.5X 011=2.0X 100=2.5X
[A2:0]=101=3.0X 110=3.5X 111=4.0X
[A3:7]=(Reserved)
[A3:6]=(Reserved)
[A3:5]=(Reserved)
[A3:4]=(Reserved)
[A3:3]=CKE Pre-driver Slew 0=Normal 1=Fast
[A3:2]=(Reserved)
[A3:1]=CKE Driving 00=1X
[A3:0]=01=2X 10=3X 11=4X
[B0:7]=Status of Hardware Trap
[B0:6]=(same as bit7)
[B0:5]=(same as bit7)
[B0:4]=(same as bit7)
[B0:3]=(same as bit7)
[B0:2]=(same as bit7)
[B0:1]=(same as bit7)
[B0:0]=(same as bit7)
[B4:7]=Status of Hardware Trap
[B4:6]=(same as bit7)
[B4:5]=(same as bit7)
[B4:4]=(same as bit7)
[B4:3]=(same as bit7)
[B4:2]=(same as bit7)
[B4:1]=(same as bit7)
[B4:0]=(same as bit7)
[B5:7]=(same as B4h bit7)
[B5:6]=(same as B4h bit7)
[B5:5]=(same as B4h bit7)
[B5:4]=(same as B4h bit7)
[B5:3]=(same as B4h bit7)
[B5:2]=(same as B4h bit7)
[B5:1]=(same as B4h bit7)
[B5:0]=(same as B4h bit7)
[B6:7]=(same as B4h bit7)
[B6:6]=(same as B4h bit7)
[B6:5]=(same as B4h bit7)
[B6:4]=(same as B4h bit7)
[B6:3]=(same as B4h bit7)
[B6:2]=(same as B4h bit7)
[B6:1]=(same as B4h bit7)
[B6:0]=(same as B4h bit7)
[B7:7]=(same as B4h bit7)
[B7:6]=(same as B4h bit7)
[B7:5]=(same as B4h bit7)
[B7:4]=(same as B4h bit7)
[B7:3]=(same as B4h bit7)
[B7:2]=(same as B4h bit7)
[B7:1]=(same as B4h bit7)
[B7:0]=(same as B4h bit7)
[B8:7]=SysDataEvenClkDly (EC) (clocks) 000=No Delay 001=0.5 RO
[B8:6]=010=1.0 011=1.5 100=2.0
[B8:5]=101=2.5 110=3.0 111=3.5
[B8:4]=SysDataOddClkDly (OC) (clocks) 000=No delay 001=0.5 RO
[B8:3]=010=1.0 011=1.5 100=2.0
[B8:2]=101=2.5 110=3.0 111=3.5
[B8:1]=SysDataEvenDly (ED) (clocks) 00=No delay RO
[B8:0]=01=0.5 10=1.0 11=Reserved
[B9:7]=SysDataOddDly (OD) (clocks) 00=No delay RO
[B9:6]=01=0.5 10=1.0 11=Reserved
[B9:5]=SysAddDly (AD) (clocks) 00=No Delay RO
[B9:4]=01=0.5 10=1.0 11=Reserved
[B9:3]=SysPushPull (PP) Drivers 0=Open drain 1=Push/Pull RO
[B9:2]=DECSysComp (DS) 0=Proc Iface w Alpha logic 1=Not RO
[B9:1]=SysDCDelay -Proc Clock Delay from data RDY until date REC RO
[B9:0]=(same as bit1)
[BA:7]=(same as B9h bit1)
[BA:6]=(same as B9h bit1)
[BA:5]=SysAddWide (EX) 0=enabled 1=disabled RO
[BA:4]=SysAddPage (PM) 0=Cache block interleave 1=Page mode RO
[BA:3]=SysAddClkDly (AC) (clocks) 000=No delay 001=0.5 RO
[BA:2]=010=1.0 011=1.5 100-2.0
[BA:1]=101=2.5 110=3.0 111=3.5
[BA:0]=SysResetClkOffset (RO) 00=Bit-time 0
[BB:7]=01=Bit-time 1 10=Bit-time 2 11=Bit-time 3
[BB:6]=SysDataRecMuxPreload (DM) Value RO
[BB:5]=(same as bit6)
[BB:4]=(same as bit6)
[BB:3]=SysAddRecMuxPreload (AM) Value RO
[BB:2]=(same as bit3)
[BB:1]=(same as bit3)
[BB:0]=BitTimesPerSysClk (BT) 0=2 Xfr/SYSCLK 1=4 Xfr/SYSCLK
[BD:7]=Address FIFO Initialze Count RO
[BD:6]=(same as bit7)
[BD:5]=Data FIFO Initialize Count RO
[BD:4]=(same as bit5)
[BD:3]=(Reserved)
[BD:2]=WrToRd Delay RO
[BD:1]=RdToWr Delay RO
[BD:0]=(same as bit1)
[BE:7]=(Reserved)
[BE:6]=(Reserved)
[BE:5]=FID Value RO 00000=11.0 00001=11.5 00010=12.0
[BE:4]=00011=12.5 00100=5.0 00101=5.5 00110=6.0
[BE:3]=00111=6.5 01000=7.0 01001=7.5 01010=8.0
[BE:2]=01011=8.5 01100=9.0 01101=9.5 01110=10.0
[BE:1]=01111=10.5 10000=3.0 10001=3.5 100104.0 10011=4.5
[BE:0]=(Reserved)
[BF:7]=(Reserved)
[BF:6]=Auto Compensation Control 0=By HW Trap 1=Disable
[BF:5]=Fixed Time S2K Compensation 0=disable 1=enable
[BF:4]=S2K Manual Compensation Offset 0=enable 1=disable
[BF:3]=NMOS S2K Compensation Offset 00=-1
[BF:2]=01=0 10=+1 11=+2
[BF:1]=PMOS S2K Compensation Offset 00=+1
[BF:0]=01=0 10=-1 11=-2
[C0:7]=(Reserved)
[C0:6]=(Reserved)
[C0:5]=(Reserved)
[C0:4]=(Reserved)
[C0:3]=(Reserved)
[C0:2]=(Reserved)
[C0:1]=(Reserved)
[C0:0]=(Reserved)
[C1:7]=AGP Major Revision (4 bits) RO
[C1:6]=(same as bit7)
[C1:5]=(same as bit7)
[C1:4]=(same as bit7)
[C1:3]=AGP Minor Revision (4 bits) RO
[C1:2]=(same as bit3)
[C1:1]=(same as bit3)
[C1:0]=(same as bit3)
[C2:7]=Next Capability (8 bits) RO
[C2:6]=(same as bit7)
[C2:5]=(same as bit7)
[C2:4]=(same as bit7)
[C2:3]=(same as bit7)
[C2:2]=(same as bit7)
[C2:1]=(same as bit7)
[C2:0]=(same as bit7)
[C3:7]=AGP Capability ID (8 bits) RO
[C3:6]=(same as bit7)
[C3:5]=(same as bit7)
[C3:4]=(same as bit7)
[C3:3]=(same as bit7)
[C3:2]=(same as bit7)
[C3:1]=(same as bit7)
[C3:0]=(same as bit7)
[C4:7]=Max AGP Requests by Sis735 (8 bits) RO
[C4:6]=(same as bit7)
[C4:5]=(same as bit7)
[C4:4]=(same as bit7)
[C4:3]=(same as bit7)
[C4:2]=(same as bit7)
[C4:1]=(same as bit7)
[C4:0]=(same as bit7)
[C5:7]=(Reserved)
[C5:6]=(Reserved)
[C5:5]=(Reserved)
[C5:4]=(Reserved)
[C5:3]=(Reserved)
[C5:2]=(Reserved)
[C5:1]=(Reserved)
[C5:0]=(Reserved)
[C6:7]=(Reserved)
[C6:6]=(Reserved)
[C6:5]=(Reserved)
[C6:4]=(Reserved)
[C6:3]=(Reserved)
[C6:2]=(Reserved)
[C6:1]=SBA Support? 0=No 1=Yes RO
[C6:0]=(Reserved)
[C7:7]=(Reserved)
[C7:6]=(Reserved)
[C7:5]=(Reserved)
[C7:4]=Fast Writes Support? 0=No 1=Yes RO
[C7:3]=(Reserved)
[C7:2]=AGP Data Rate (4X) RO
[C7:1]=(same as bit2)
[C7:0]=(same as bit2)
[C8:7]=(Reserved)
[C8:6]=(Reserved)
[C8:5]=(Reserved)
[C8:4]=(Reserved)
[C8:3]=(Reserved)
[C8:2]=(Reserved)
[C8:1]=(Reserved)
[C8:0]=(Reserved)
[C9:7]=(Reserved)
[C9:6]=(Reserved)
[C9:5]=(Reserved)
[C9:4]=(Reserved)
[C9:3]=(Reserved)
[C9:2]=(Reserved)
[C9:1]=(Reserved)
[C9:0]=(Reserved)
[CA:7]=(Reserved)
[CA:6]=(Reserved)
[CA:5]=(Reserved)
[CA:4]=(Reserved)
[CA:3]=(Reserved)
[CA:2]=(Reserved)
[CA:1]=SBA Enable 0=disable 1=enable
[CA:0]=AGP Enable 0-disable 1=enable
[CB:7]=(Reserved)
[CB:6]=(Reserved)
[CB:5]=(Reserved)
[CB:4]=FW Enable 0=disable 1=enable
[CB:3]=(Reserved)
[CB:2]=Data Rate 001=1X 010=2X 100=4X XXX=Reserved
[CB:1]=(same as bit2)
[CB:0]=(same as bit2)
[D0:7]=(Reserved)
[D0:6]=(Reserved)
[D0:5]=(Reserved)
[D0:4]=(Reserved)
[D0:3]=CPU-to-PCI Front-end retry 0000=1 Retry 0010=3 Retries
[D0:2]=(same as bit3)
[D0:1]=(same as bit3)
[D0:0]=(same as bit3)
[D1:7]=Host Bridge/AGP Burst Cycles 0=enable* 1=disable
[D1:6]=AGP Post Write Combines 0=enable* 1=disable
[D1:5]=Config to Special Conversion 0=enable* 1=disable
[D1:4]=FW Data Transfer Mode 0=Normal* 1=Test
[D1:3]=Dummy CPU/AGP Cycle Filter 0=disable 1=enable
[D1:2]=(Reserved)
[D1:1]=(Reserved)
[D1:0]=(Reserved)
[D2:7]=(Reserved)
[D2:6]=(Reserved)
[D2:5]=CPU to AGP Access Latency 0=Normal 1=Fast*
[D2:4]=CPU/AGP Back to Back Performance 0=Normal 1=Fast*
[D2:3]=(Reserved)
[D2:2]=AGP 4X Capability 0=enable 1=disable
[D2:1]=AGP FW Capability 0=enable 1=disable
[D2:0]=AGP Master BMREQ Map 0=No AGP Mapping 1=AGP Maps to BMREQ
[D3:7]=735/AGP Read Grant Threshold 00=1 block
[D3:6]=01=2 blocks 10=4 blocks 11=8 blocks
[D3:5]=Read Grant Pipeline Control 0=Fast 1=Slow
[D3:4]=AGP Write Flush 0=Flush low priority 1=Flush low and high
[D3:3]=AGP Stage Control Reset 0=De-assert reset 1=Assert reset
[D3:2]=AGP Counter Test 0=Normal 1=Test mode
[D3:1]=AGP/PCI Pipeline 0=Slow 1=Fast
[D3:0]=TRDY# Data Transfer Delay 0=Min Delay 1=Max Delay
[D4:7]=(Reserved)
[D4:6]=(Reserved)
[D4:5]=(Reserved)
[D4:4]=(Reserved)
[D4:3]=Read Partition Size 0=4QW 1=8QW
[D4:2]=Abort Disconnect. Delayed Transact. 0=disable* 1=enable
[D4:1]=Allow only same PCI66 Read CMD 0=disable* 1=enable
[D4:0]=PCI66 Mem Read Prefetch 0=disable 1=enable
[D5:7]=Value of PCI66 Discard Timer, Delayed Transaction (16 bits)
[D5:6]=(same as bit7)
[D5:5]=(same as bit7)
[D5:4]=(same as bit7)
[D5:3]=(same as bit7)
[D5:2]=(same as bit7)
[D5:1]=(same as bit7)
[D5:0]=(same as bit7)
[D6:7]=(same as D5H bit7)
[D6:6]=(same as D5H bit7)
[D6:5]=(same as D5H bit7)
[D6:4]=(same as D5H bit7)
[D6:3]=(same as D5H bit7)
[D6:2]=(same as D5H bit7)
[D6:1]=(same as D5H bit7)
[D6:0]=(same as D5H bit7)
[D8:7]=Initial Value for APRT Timer (in AGP Clocks)
[D8:6]=(same as bit7)
[D8:5]=(same as bit7)
[D8:4]=(same as bit7)
[D8:3]=(same as bit7)
[D8:2]=(same as bit7)
[D8:1]=(same as bit7)
[D8:0]=(same as bit7)
[D9:7]=Initial Value for DPT Timer (in AGP Clocks)
[D9:6]=(same as bit7)
[D9:5]=(same as bit7)
[D9:4]=(same as bit7)
[D9:3]=(same as bit7)
[D9:2]=(same as bit7)
[D9:1]=(same as bit7)
[D9:0]=(same as bit7)
[DA:7]=Data Transfer Counter (DTC)
[DA:6]=(same as bit7)
[DA:5]=(same as bit7)
[DA:4]=(same as bit7)
[DA:3]=Write Buffer Flush Counter (WBFC)
[DA:2]=(same as bit3)
[DA:1]=(same as bit3)
[DA:0]=(same as bit3)
[DC:7]=Manual Calibration Driving Strength
[DC:6]=(same as bit7)
[DC:5]=(same as bit7)
[DC:4]=(same as bit7)
[DC:3]=(same as bit7)
[DC:2]=(same as bit7)
[DC:1]=(same as bit7)
[DC:0]=(same as bit7)
[DD:7]=Calibration Control 0=Value from RDCb 1=Automatic Generation
[DD:6]=AGP Buffer Slew Rate 0=Fast 1=Slow
[DD:5]=Input Buffer Type 0=Differential 1=Bypass/Single-ended
[DD:4]=(Reserved)
[DD:3]=Automatic Calibration (see bit7) 0=disable 1=enable
[DD:2]=Calibration Interval 00=5ms
[DD:1]=01=10ms 10=20ms 11=40ms
[DD:0]=(Reserved)