EVGA nForce 680i SLI - Table 7. On-Board LED POST Codes - Code (hex)
hallo. ich hab ein 680i von XFX aber da XFX genau wie EVGA nur ein firmenlogo auf die von nvidia gefertigten boards haut und es dann verkauft, ist das ja egal.
also ich hab das problem, dass ich es gestern eingebaut habe und der led post code panel gleich nen fehler brachte und zwar "Fd" leider habe ich nirgens etwas über die bedeutung der codes gefunden. ich vermute es liegt daran, dass noch kein ram drin ist denn den bekomm ich erst im laufe der woche. also kann mir jemand sagen, was Fd zu bedeuten hat und mir ev. ne liste mit allen codes und deren bedeutung nennen ?
No Problem & für die - die dies schon immer mal benötigten
EVGA nForce 680i SLI - Table 7. On-Board LED POST Codes - Code (hex)
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01 Reserved
02 Jumps to E000 segment Execution of POST routines in E000
03 Early Superio Init Early Initialized the super IO
04 Reserved
05 Blank video Reset Video controller
06 Reserved
07 Init KBC Keyboard controller init
08 KB test Test the Keyboard
09 Reserved
0A Mouse Init Initialized the mouse
0B Reserved
0C Reserved
0D Reserved
0E CheckSum Check Check the integrity of the ROM,BIOS and message
0F Reserved
10 Autodetect EEPROM Check Flash type and copy flash Write/erase routines
11 Reserved
12 Test CMOS Test and Reset CMOS
13 Reserved
14 Load Chipset Load Chipset Defaults
15 Reserved
16 Init Clock Initialize onboard clock generator
17 Reserved
18 InitCPU CPU ID and initialize L1/L2 cache
19 Reserved
1A Reserved
1B Setup Interrupt Initialize first 120 interrupt vectors Vector Table with
SPURIOUS_INT_HDLR and initialize INT 00h-1Fh according to INT_TBL
1C CMOS Battery Check Test CMOS and check Battery Fail
1D Early PM Early PM initialization
1E Reserved
1F Re-initial KB Load keyboard matrix
20 Reserved
21 HPM init Init Heuristic Power Management (HPM)
22 Reserved
23 Program chipset Early Programming of chipset registers
24 Init PNP Init PNP
25 Shadow VBIOS Shadow system/video BIOS
26 Clock Gen Init onboard clock generator and sensor
27 Setup BDA Setup BIOS DATA AREA (BDA)
28 Reserved
29 CPU Speed detect Chipset programming and CPU Speed detect
2A Reserved
2B Init video Initialize Video
2C Reserved
2D Video memory test Test Video Memory and display Logos
2E Reserved
2F Reserved
30 Reserved
31 Reserved
32 Reserved
33 Early keyboard reset Early Keyboard Reset
34 Reserved
35 Test DMA Controller 0 Test DMA channel 0
36 Reserved
37 Test DMA Controller Test DMA channel 1
38 Reserved
39 Test DMA Page Registers
3A Reserved
3B Reserved
3C Test Timer Test 8254 Timer 0 Counter 2.
3D Reserved
3E Test 8259-1 Mask Verify 8259 Channel 1 masked interrupts by alternately
turning off and on the interrupt lines.
3F Reserved
40 Test 8259-2 Mask Verify 8259 Channel 2 masked interrupts by alternately turning off and on the interrupt lines.
41 Reserved
42 Reserved
43 Test Stuck Interrupt Turn off interrupts then verify no 8259's Interrupt mask register is on. Test 8259 Force an interrupt and verify the interrupt occurred.
44 Reserved
45 Reinit serial port Reinitialize Preboot agent serial port
46 Reserved
47 EISA Test If EISA non-volatile memory checksum is good, execute EISA initialization. If not, execute ISA tests and clear EISA mode flag.
48 Reserved
49 Size Memory Size base memory from 256K to 640K and extended memory above 1MB.
4A Reserved
4B Reserved
4C Reserved
4D Reserved
4E Init APIC Initialize APIC and set MTRR
4F Reserved
50 USB init Initialize USB controller
51 Reserved
52 Memory Test Test all memory of memory above 1MB using Virtual 8086mode, page mode and clear the memory
53 Reserved
54 Reserved
55 CPU display Detect CPU speed and display CPU vendor specific version string and turn on all necessary CPU features
56 Reserved
57 PnP Init Display PnP logo and PnP early init
58 Reserved
59 Setup Virus Setup virus protect according to protect setup
5A Reserved
5B Awdflash Load If required, will auto load Awdflash. exe in POST
5C Reserved
5D Onboard I/O Init Initializing onboard superIO
5E Reserved
5F Reserved
60 Setup enable Display setup message and enable setup functions
61 Reserved
62 Reserved
63 Initialize Mouse Detect if mouse is present, initialize mouse, install interrupt vectors.
64 Reserved
65 PS2 Mouse special Special treatment to PS2 Mouse port
66 Reserved
67 ACPI init ACPI sub-system initializing
68 Reserved
69 Init Cache Initialize cache controller
6A Reserved
6B Setup Enter setup check and auto configuration check up
6C Reserved
6D Initialize Floppy Initialize floppy disk drive
6E Reserved
6F FDD install Install FDD and setup BIOS data area parameters
70 Reserved
71 Reserved
72 Reserved
73 Initialize Hard Drive Initialize hard drive controller
74 Reserved
75 Detect HDD IDE device detection
76 Reserved
77 Detect serial ports Initialize serial ports
78 Reserved
79 Reserved
7A Detect parallel ports Initialize parallel ports
7B Reserved
7C HDD Write Protect HDD check for write protection
7D Reserved
7E Reserved
7F POST error check Check POST error and display them and ask for user intervention
80 Reserved
81 Reserved
82 Security Check Ask password security.
83 Write CMOS Write all CMOS values back to RAM and clear screen
84 Display PNP Display PNP devices
85 USB Final Init Final USB initialization
86 Reserved
87 Reserved
88 Reserved
89 Setup ACPI tables Setup ACPI tables
8A Reserved
8B Option ROM Detect Scan for Option ROMs
8C Reserved
8D Enable Parity Check Enable Parity Check
8E Reserved
8F IRQ12 Enable Enable IRQ12 if mouse present
90 Reserved
91 Reserved
92 Reserved
93 Boot Medium Read Detect and store boot partition head and cylinders values in RAM
94 Final Init Final init for last micro details before boot
95 NumLock Set NumLock status according to Setup
96 Boot Attempt Set low stack Boot via INT 19h.
C0 Base CPU test Read/Write CPU registers
C1 Memory Presence Base memory detect
C2 Early Memory Board Initialization
C3 Extend Memory Turn on extended memory, cache initialization
C4 Special Display First display initialization
C5 Early Shadow Early shadow enable for fast boot
C6 Cache presence External cache s
FF Boot
F0 HW Ident Identify HW in the system
F1 SLAM Table Register the slam tables
F2 Early SLAM table Early SLAM table
F3 Init Com Port COM port initialization
00 HW Init Initialize hardware devices
01 Override Parameters Override input parameters etc. before QUERY
04 Process SPD Read SPD & fill in arrays
08 Query HW Query the hardware devices
0C Load ROM Table ROM table pointer
10 Init Memory Controller Initialize the Memory Controller
11 Init Memory Controller PLL Init
12 Init Memory Controller Query after Memory PLL has been set
13 Init Memory Controller Set Dynamic SPD values
14 Init Memory Controller Load Memory Info Structure
15 Init Memory Controller Load DIMM geometry (using SPD)
16 Init Memory Controller Prepare MRS variables
17 Init Memory Controller Probe memory geometry
18 Init Memory Load PROD and PROD_C tables Controller
19 Init Memory Controller ProdD – Discrete assembly register init algorithms
1A Init Memory Controller ProdE – ProdC + Expandable criteria
1B Init Memory Controller Send EMRS/MRS configuration cycles
1C Init Memory Controller Overvoltage handling
1D Init Memory Controller ProdF – final, ladder and wallclock algorithms
20 Init PCI Express PCI Express Initialization
23 Init PCI Express Release XReset 30 Init Spread Spectrum Load Spread Spectrum tables
31 Init Spread Spectrum Set CPUPLL Override
32 Init Spread Spectrum Set m/n/p value
33 Init Spread Spectrum Enable CPU Spread Spectrum
40 Set Top-Of-Memory Set Top-Of-Memory registers
44 Late SLAM table Late SLAM table
48 Previous Power State Previous Power State SLAM SLAM table table
4C Hardware Workarounds Hardware Workarounds
50 NVMM Restore, and exit NVMM
54 NV Memory Test NV Memory Test
FE ERROR handler ERROR handler
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@Water-PhoeniX - ein Fd so wie Du es beschreibst ist leider nicht dabei, aber ich nehme doch auch mal schwer an, das dies heissen soll, dass Du noch keine Rams drinne hast
Greetz Mike
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