[Sammelthread] Intel DDR5 RAM OC Thread

[tibcsi0407]

?

Nope iot was 40/48 on both.

Tried 40-34 34-40 on first slot

 

[Veii]

Nope iot was 40/48 on both.

Tried 40-34 34-40 on first slot

48-40-40-48 maybe ?

 

[tibcsi0407]

48-40-40-48 maybe?

I tried that first, Y stuck, posted a pic.
Maybe a retrain would be enough, will try it again as the slot B will finish the current run.

Haha, it finished very soon.

40/34 34/40 is no bueno.

 

[Veii]

will try it again as the slot B will finish the current run.

hmmm

Eh at the end its 9*2 combinations
You got this.

2nd MC needs a lower value vs first.
but thats about it.

 

[tibcsi0407]

hmmm

Eh at the end its 9*2 combinations
You got this.

2nd MC needs a lower value vs first.
but thats about it.

It died in both slots, so I guess I need higher impedance.
What I noticed that the dimms are using more power during Y if only only one slot is enabled.

 

[Veii]

Haha, it finished very soon.

You know
for this typical bruteforce does well : ')
A spreadsheet

its not many combinations, 34/40/48 * 4
optimally 2nd MC is weaker
And optimally they are reverse-mirrored

 

[tibcsi0407]

You know
for this typical bruteforce does well : ')
A spreadsheet

its not many combinations, 34/40/48 * 4
optimally 2nd MC is weaker
And optimally they are reverse-mirrored

We will see, but I believe we are close.

First slot finished on 48/40 - 40/48

Starting to test the second slot.

 

[Veii]

I tried that first, Y stuck, posted a pic.

First slot finished on 48/40 - 40/48

Soo just 2nd keeps failing ?
Or i missunderstand you 🤭

If 2nd fails on 48-40-40-48 (likely can)
You can try a 48-40-40-40 or even a 48-40-40-34
But i don't think that would do good.

Its bed time for me
Best of success
and i guess if you have plenty of time and finish testing on whatever survives longest

go for CTL1 CtlVref first value 150 , then value 141
Coldboot so it retrains - but only if you are happy with RONs.
For that you'd like to attempt full layout testing.

Any case, its a bonus and shouldnt be done. // one CTL1 value alone is bad, although helpful
But just so you have "work" to do : ') ~ in case you finish faster.
Would be interesting to see.

We may need to mess with VDDQ_CPU when messing with RONs
But getting that training variable away is a good idea.
If you are undecided between 2-3 values. Then longer runtime is required before moving on.

Beitrag automatisch zusammengeführt: 06.02.2024

Be sure that RON Training is off~

 

[tibcsi0407]

Soo just 2nd keeps failing ?
Or i missunderstand you 🤭

If 2nd fails on 48-40-40-48 (likely can)
You can try a 48-40-40-40 or even a 48-40-40-34
But i don't think that would do good.

Its bed time for me
Best of success
and i guess if you have plenty of time and finish testing on whatever survives longest

go for CTL1 CtlVref first value 150 , then value 141
Coldboot so it retrains - but only if you are happy with RONs.
For that you'd like to attempt full layout testing.

Any case, its a bonus and shouldnt be done. // one CTL1 value alone is bad, although helpful
But just so you have "work" to do : ') ~ in case you finish faster.
Would be interesting to see.

We may need to mess with VDDQ_CPU when messing with RONs
But getting that training variable away is a good idea.
If you are undecided between 2-3 values. Then longer runtime is required before moving on.

Beitrag automatisch zusammengeführt: 06.02.2024

Be sure that RON Training is off~

Nope, the first slot failed yesterday what setting, today it's passed. I retrained again and it's good now.
Now the second slot under testing.
Then I will set the Ctlvrefup as you suggested.

Thank you and have a nice rest. 😊


Update

Second slot passed too.
VST is slower on this one. VT3 is the same. Interesting.

@Veii

Some update, both channels passed. I set RON 48-40-40-48 agaiin and reduced TX to 1.32V
Unfortunately I had no time for longer test yet, but I will run a 90 miinutes test in the afternoon too.
The CTL1 is still on Auto. No RX-DFE
CPU is on LLC3 with IA_AC 0.65 and custom V/F curve.

I am happy to our collaboration, I couldn't reach this without your help.
The long term stability is still a quetion, but we are closer than ever.

Update

It was only stable only until next reboot. More work left.
RTT tuning is next?

 

[zebra_hun]

Ich habe 8000 von Anfang total neu gemacht. Was ich nicht verstehe, Bits/sec sind extreme gut. Jetzt mehr Vcore, deswegen statt 55x ist 56x, Ron von Tibcsi statt 34/34 ist 48-40 - 40-48.
Vielleich hat Jemand gute Idee, die ich nich sehe oder kapiere.
Danke
BIOS

****Update***
Auf diesen Settings habe ich TM5 auch probiert.
+2 Screenshot noch dazu. Ein Bild ist unter TM5 25. Cycle, und ein Bild wenn finish ist.

 

[perlibu]

Nimm das angehängte TM5.
Die config ist anders. Das Programm ist anders.
Hat 1usmus_v3 zu sein.

Habe es nochmals runtergeladen. Kommen errors beim Anta Profil beim Starten. Also TM5 startet es gar nicht. Hab keine Ahnung wieso.

Edit:
habe VDDQ training aus, IVR TX VDD auf 1.415v gestellt. MRC Fastboot off, MCH On.
SA und VDD gefixt, rest auf Auto.
RRD_SG auf 68
RRD_DG auf 50
RFCpb auf 576
RFC2 ist 672( in 32er steps)

WTRL auf 30, zeigt aber 28 an
WTRS auf 12, zeigt 10 an.

ycruncher gestartet. Error
Habe auch WTRL auf 24 und WTRS auf 8, dafür Auto bei RRD_SG und DG. beides zu error.

 

[Vhypur]

@Veii how does this look? i have a couple profiles/curves saved since i've been messing with them off and on over the last 3 or so days (1 of the other profiles i have saved is very a similar curve but has another drop at 5.6 which this curve i'm posting now basically just has 5.6 straightened out, but maybe the other curve with another drop at 5.6 is better?)

 

[Veii]

@Veii

Some update, both channels passed. I set RON 48-40-40-48 agaiin and reduced TX to 1.32V
Unfortunately I had no time for longer test yet, but I will run a 90 miinutes test in the afternoon too.
The CTL1 is still on Auto. No RX-DFE
CPU is on LLC3 with IA_AC 0.65 and custom V/F curve.

I am happy to our collaboration, I couldn't reach this without your help.
The long term stability is still a quetion, but we are closer than ever.

Holy VID
Now there is no way you don't hit PL4~

Update

It was only stable only until next reboot. More work left.
RTT tuning is next?

Was afraid that Groups & RON Play together
But it shouldnt.

Its you messing with voltage, very likely.
But i dont think we are anywere near done with RON topic.

Those are values for near identical behavior.
And purposely weak
Its not values for per channel behavior.

Update

Second slot passed too.
VST is slower on this one. VT3 is the same. Interesting.

I'm slightly afraid its due to VID throttle.
But better throttle vs cpu instability.

You need to verify current stability for longer duration
Make a docs/excel sheet and track longer if both channels are now kind of similar in behavior
48-40 is weak.
Its ok but its purposely selected weak.

I cant say "its good" yet.
No CTL1 foolery for now.

It was only stable only until next reboot. More work left.
RTT tuning is next?

RTT on Gear 4
I wouldnt now
Too many variables

With RON you are at 30% of what you should and can change.
Its too early.
Those are not long term stable results.
Groups are next before starting with Groups+RTT.

But RON is not done for your Board.
I hope you havent forgotten RON training-off.

I would apply the RTL and _DR off, parts tho.
Because you run them on off but mem tries to use _DR.

Ron von Tibcsi statt 34/34 ist 48-40 - 40-48.

RON are PCB exclusive and capacity focused.
Do not copy.

ycruncher gestartet. Error

Das macht VDDQ Training OFF, für dich
Spannungen sind unpassend = error.

VDDQ_CPU auf 1.38, vorerst.
tWRRD oder WTR, nicht beides zusammen.

 

[Veii]

@Veii how does this look? i have a couple profiles/curves saved since i've been messing with them off and on over the last 3 or so days (1 of the other profiles i have saved is very a similar curve but has another drop at 5.6 which this curve i'm posting now basically just has 5.6 straightened out, but maybe the other curve with another drop at 5.6 is better?)

Anhang anzeigen 968008

Ignore clock. It means nothing

I dont like those
But what matters is not my word or visually.

Sure you can "just trust me"
But i trust only results.
Cinebench R23 & R15 Extreme
Geekbench 3 & latest
And PyPrime 2b
// potentially SiSoftware Sandra InterThread or Core2Core Bench

Track scaling there,
Ignore clockstrap or even effective clock.
It doesn't translate to actual perf.
A lot of things are load balanced.

 

[Vhypur]

Ignore clock. It means nothing
Anhang anzeigen 968163Anhang anzeigen 968164
I don't like those
But what matters is not my word or visually.

Sure you can "just trust me"
But I only trust results.
Cinebench R23 & R15 Extreme
Geekbench 3 & latest
And PyPrime 2b
// potentially SiSoftware Sandra InterThread or Core2Core Bench

Track scaling there,
Ignore clockstrap or even effective clock.
It doesn't translate to actual perf.
A lot of things are load balanced.

Ok thanks i'll take a look at some more stuff, as of right now its stable on all of those but i gotta test PyPrime 2b still, also i'm assuming you want point 1 and or 2 to come up so it isn't so close to 700mhz? and how about the top 1 or 2 v/f points? would those be best smoothened out like the points before or should v/f 11 drop a bit further closer to v/f 10?

 

[Veii]

Was afraid that Groups & RON Play together
But it shouldnt.

Its you messing with voltage, very likely.
But i dont think we are anywere near done with RON topic.

Those are values for near identical behavior.
And purposely weak
Its not values for per channel behavior.

Now i understand you @tibcsi0407

ok ok.

Well RON is purposely weakened because i expect Encore to handle this
I dont expect WhiteApex to handle this.
They are just different PCBs.

Beitrag automatisch zusammengeführt: 07.02.2024

also i'm assuming you want point 1 and or 2 to come up so it isn't so close to 700mhz?

700mV is your floor.
Don't trust that every CPU will be able to handle 700mV floor.
I dont know substrate too well. Very much not.

We want headroom, because once you start to shift AC_LL - it can easily shift under 700mV
720 is a good place to stay an rather i dislike the shape. Its ok to be near flat or have a small bump.

Top two , the spike bothers me
too much delta between values.
What AC_LL are we on ?

 

[Vhypur]

Now I understand you @tibcsi0407
Anhang anzeigen 968171
OK, OK.

Well RON is purposely weakened because I expect Encore to handle this
I don't expect WhiteApex to handle this.
They are just different PCBs.

Beitrag automatisch zusammengeführt: 07.02.2024

700mV is your floor.
Don't trust that every CPU will be able to handle 700mV floor.
I don't know substrate too well. Very much not.

We want headroom, because once you start to shift AC_LL - it can easily shift under 700mV
720 is a good place to stay an rather i dislike the shape. It's ok to be near flat or have a small bump.

Top two, the spike bothers me
too much delta between values.
What AC_LL are we on?

Ok i'll def move the floor up and try to bring the top 2 spikes atleast closer together, I know somewhere back you said you want something like a double S right? - this is on LLC4

 

[Veii]

I know somewhere back you said you want something like a double S right? - this is on LLC4

Ceiling is complicated, because you work on a curvepoint that you have running clocks on
Yet if you target higher TVB clock, then you reach faster VID ceiling.

Soo i like top to be slightly smoothed out, rather slightly dropping downwards
As effects extrapolate on curvepoints you dont see

 

[tibcsi0407]

oly VID
Now there is no way you don't hit PL4~

Accc. to Hwinfo it doesn't hit it. The last point boost wants a lot of Vid.

You need to verify current stability for longer duration
Make a docs/excel sheet and track longer if both channels are now kind of similar in behavior
48-40 is weak.
It's ok but its purposely selected weak.

I need some time for that, but we are not in a hurry. I have a lot of work in the job.

What makes me angry that it can't run 1 cycle now at all. When I change TX and retrain (I use the retrain button, that is like power off and on) it can run for a while.
Yesterday I changed TX to 1.35V and ran 20 minutes on Y.
Is this DQS related issue?

RTL's were on auto for me, that's why I didn't zero out the DR and DD values. Tought maybe I will change it on the end of the tuning.

 

[Veii]

RTL's were on auto for me, that's why I didn't zero out the DR and DD values. Tought maybe I will change it on the end of the tuning.

Maybe i remember that some said a zero some said 25.
mm mm
yea you can keep it how it is, but if you zero RTL , then zero DR .
If you zero R1 and R3, not only R4-R7, then zero DD timings too.

What makes me angry that it can't run 1 cycle now at all. When I change TX and retrain (I use the retrain button, that is like power off and on) it can run for a while.
Yesterday I changed TX to 1.35V and ran 20 minutes on Y.
Is this DQS related issue?

The problem is,
RONs mess with voltages
VDDQ's are the key building block for

Everything depends on them.
All Slopes , remain ODTs
Its the main Vref building block.

Delta inside mem doesnt need to exist.
It can, i like it but its just me.
I like the benefit it gives to lower VDDQ_CPU

But
Low VDDQ_CPU still requires good PCB quality.
Outside of user (A) matching by the board without automatic training
It still is at the mercy of the Mainboard PCB itself and at the mercy of all other potential noise that will mess with it.

Soo the first mistake will be changing only VDDQ_CPU , but not adapting VDDQ_MEM
Another is that VDDQ_CPU changes, need cold boots.
Far too many things depend on this value, soo it might not train clean.

Else messing with SA and VDD2, is the way to go if you change VDDQ_CPU.

---

Given we never finished with RON testing (for your pcb)
it was far too early to change other variables.
Correct approach was rather to fix RONs

 

[tibcsi0407]

Maybe I remember that someone said a zero someone said 25.
mm mm
yes you can keep it how it is, but if you zero RTL, then zero DR.
If you zero R1 and R3, not only R4-R7, then zero DD timings too.


The problem is,
RONs measure with voltages
VDDQ's are the key building block for
Anhang anzeigen 968175
Everything depends on them.
All slopes remain ODTs
Its the main Vref building block.

Delta inside mem doesn't need to exist.
It can, I like it but it's just me.
I like the benefit it gives to lower VDDQ_CPU

But
Low VDDQ_CPU still requires good PCB quality.
Outside of user (A) matching by the board without automatic training
It still is at the mercy of the Mainboard PCB itself and at the mercy of all other potential noise that will mess with it.

So the first mistake will be changing only VDDQ_CPU , but not adapting VDDQ_MEM
Another is that VDDQ_CPU changes, need cold boots.
Far too many things depend on this value, so it might not train clean.

Else messing with SA and VDD2, is the way to go if you change VDDQ_CPU.

---

Given we never finished with RON testing (for your pcb)
it was far too early to change other variables.
Correct approach was rather to fix RONs

Yes, that's right but MEM_VDDQ never ever was nice under 1.47V for me.
Maybe I have to choose the other way and reduce the mem delta with raising VDDQ.
Lower RON was not good with the current voltage set. Maybe I need to revise the whole thing.

@Veii
Update

Tried lower RON's, but it's no good.
Set 48/48-48/48 out of couriousity

I will try a cold boot now, if it won't drop me out in the beginning, maybe it can be a good way. Maybe MC1 can be stronger, need to play with the possibilities.
Bitrates are not constant, so maybe playing with MC's could help, I will try it. Actually this is fun!

It can run 10+ minutes again. I had to play the V/F 58X a little, because when the water is too cold (AC on atm), the cores are jumping to 58X sometimes and the Vcore is not enough.
Anyway, it's a bit closer.
I will do one more retrain, this time with warmer water.

 

[perlibu]

Das macht VDDQ Training OFF, für dich
Spannungen sind unpassend = error.

VDDQ_CPU auf 1.38, vorerst.
tWRRD oder WTR, nicht beides zusammen.

Soll ich also das VDDQ Training ausmachen?
werd die VDDQ CPU auf 1.38 stellen.

Ich habe beide Varianten versucht.
WTRL auf 30, zeigt aber 28 an
WTRS auf 12, zeigt 10 an.

Habe auch WTRL auf 24 und WTRS auf 8, dafür Auto bei RRD_SG und DG. ODER eben WTRL 28, WTRS 12 und RRD_SG 68, RD 50. Beides gab errors.

 

[Veii]

Soll ich also das VDDQ Training ausmachen?
werd die VDDQ CPU auf 1.38 stellen.

Ich habe beide Varianten versucht.
WTRL auf 30, zeigt aber 28 an
WTRS auf 12, zeigt 10 an.

Habe auch WTRL auf 24 und WTRS auf 8, dafür Auto bei RRD_SG und DG. ODER eben WTRL 28, WTRS 12 und RRD_SG 68, RD 50. Beides gab errors.

ATC hat ein auslese Problem.

VDDQ Training muss auf aus, damit man seine korrekte VDDQ zu VDDQ findet.

"Gab error" bedeuted für mich nichts.

 

[perlibu]

ATC hat ein auslese Problem.

VDDQ Training muss auf aus, damit man seine korrekte VDDQ zu VDDQ findet.

"Gab error" bedeuted für mich nichts.

Ok, das erklärts. Wie in meinem Post, wo ich den Screen postete vom error ycruncher.

Hab jetz mal WTRL auf 24 und WTRS auf 8 gestellt. Die RRD auf auto. vddq auf 1.38, training aus. Versuche mal.
edit:
auch error.

 

[tibcsi0407]

@Veii
More playing with the 48/48 - 48/48 RON set.
Raised VDDQ_MEM to 1.35V, reduced VDD2 to 1.512V.
One more step forward.
Bitrates are nice and constant. Strange, it didn't even lowered before the crash.
Dunno, could be the ring too. It switches sometimes between 49-50X. If I give a little offset to the adaptive ring SVID it runs on 50X constantly, error comes faster. With more Vcore it shouldn't be an issue, but I don't want to overvolt it.

Tought maybe I should run TM5 to analyze where the error comes from, but it is still freezing at 45-50 min without any error. Really strange. Maybe I should reflash the BIOS.
Now turned off TVB and running the test without that to make sure it's not my V/F curve.

 

[Veii]

Something from me to share
Spreading gossip
~ silly low voltage testing on a Board he always disliked, on his timings with my methods

1.38v V/F
OEM greens.

Not passing actual 70-80° mem tortute and Bios 0081 still has reboot inconsistencies.
But its progress & ODT PoC~

 

[tibcsi0407]

Something from me to share
Spreading gossip
~ silly low voltage testing on a Board he always disliked, on his timings with my methods
Anhang anzeigen 968266
1.38v V/F
OEM greens.

Not passing actual 70-80° mem tortute and Bios 0081 still has reboot inconsistencies.
But its progress~

Good job!
The VDDQ_CPU is really nice and low! With P SP118 this CPU should be a beast too.

 

[Veii]

Good job!
The VDDQ_CPU is really nice and low! With P SP118 this CPU should be a beast too.

He has two.
A 14600K godbin @ 1.2 v/f
And a 14900K godbin @ 1.38 v/f but with SA (load) bug.
No VDD2 bug tho

14900K was bit better than sugi's
But it has an SA freeze bug above 1.25-1.28v.
Even if it can start with my 1.35/1.48 SA/MC preset

 

[snakeeyes]

Something from me to share
Spreading gossip
~ silly low voltage testing on a Board he always disliked, on his timings with my methods
Anhang anzeigen 968266
1.38v V/F
OEM greens.

Not passing actual 70-80° mem tortute and Bios 0081 still has reboot inconsistencies.
But its progress & ODT PoC~

Txvddq ist mal echt extrem niedrig. Nett und das bei 2x16.

 

[tibcsi0407]

14900K was bit better than sugi's
But it has an SA freeze bug above 1.25-1.28v.
Even if it can start with my 1.35/1.48 SA/MC prese

This is really annoying. My max is 1.235V, 1.24 could already freeze in TM5.