[Sammelthread] Intel DDR5 RAM OC Thread

[Veii]

I dont think i can mount the block any better sadly, so im out of ideas

Those at worst can be 1-2 screws and need little loosening
You can do that in runtime and test.
But for now its ok, lets establish an actual baseline first.

EDIT:
I wish you wouldnt run HT-off, as there are better ways to handle scheduler assignment and will hide instability
But that also can wait a bit. Lets keep results consistent

 

[Darkthrone]

Im not sure if those are Class V A-dies, or they are old enough to be high binned ClassA

But please input:
RTT_WR 48,
NOM both to 80,
RTT_PARK to 40,
PARK_DQS to 48

That can run y-cruncher for 5 loops
And can run full TM5 suite
That should be then fine as your full baseline

I hope it passes else needs RTT_PARK & DQS change.
But voltages are just where they should be
Attached old VirusReport-Free TM5

Is there anything i can post for you to check the Class of the dimms? I dont even know what is that

So 5 loops of VST/VT3 and full 25 loops of TM5?
This will take some time...so lets start!

Do I have to change something in the Memory Training Algorithms also? 🤔

 

[tibcsi0407]

Also this is insane , haha.
Be careful - at 300mV drop (due to under-/overshoot), PMIC and supply design might reach a limit.
According to specifications it will.

It's a huuuuuge delta. But it handles it very good. I ran some tests before but it always crased at 12-16 min after every retrain. My tRFCpb was too tight.
Didn't run TM5 yet, because my Windows kills every version for some reason, I will do it later.

I will try the insta crash test, just I am in a project right now.

 

[Veii]

Is there anything i can post for you to check the Class of the dimms? I dont even know what is that

So 5 loops of VST/VT3 and full 25 loops of TM5?
This will take some time...so lets start!

Ah its only written on the ICs sadly.
Early we had RamMon by Passmark.
but they updated it and now it doesnt display correctly the JEDEC binning of the ICs.

Some bad ICs are JEDEC 4800 binned although follow A-Die 120ns RFC cap instead ~135-140ns M-Die.
The ICs Branding next to the manufacturing date 2xxA, 2xxV, 300A, 300V
A is Class A, V are the lower tier of cheaper to produce ICs. With slight disadvantage on primaries, RTP and RFC.
Well the biggest is their clock limit. Most cap near 7800 where afterwards they want a lot of voltage.
Real class-A can easily go higher without having to tighten down primaries soo much

In the current buying state, everything from 5600-7800 kits can be ClassV
Its difficult.
Else if your TeamGroups are - TG silk, vs SK Hynix branded ~ they are 3xx versions and pretty much ClassV.
Ellse they wouldnt have a reason to buy cheap and to also hide it.

I dont have any tight profile for A-Dies sadly
Except low clock.

So 5 loops of VST/VT3 and full 25 loops of TM5?
This will take some time...so lets start!

Shouldnt be too bad
5 loops to verify our change doesnt break anything on cpu side
And then full TM5, yes ~ but that takes for you around 90min too. 1:30-1:50h
Might take near that 1:45-1:50 mark, as you run HT off.

Let me know if RTT, especially PARK side refuses to boot.
ASUS is known to reinvent the wheel, especially on RTTs + Board design , so lets see.
Same usually for G.Skill PCBs
Change should "just work".

RTTs for both channel are identical and not compatible with 24GB dimms.

Beitrag automatisch zusammengeführt: 29.05.2024

I will try the insta crash test, just I am in a project right now.

still investigating ODT issues, of samples.
But i'm curious how much of it was user-error to begin with.

Happy ppl start to listen to me on PMIC side and VDDQ off side
Just taken, soon ~2? years.
Happy everyone starts to listen with limiters too.
Maybe slowly things change. But very slowly.

 

[tibcsi0407]

still investigating ODT issues, of samples.
But i'm curious how much of it was user-error to begin with.

I don't think there are user errors in this case. For me TM5 freezes after some cycles when I am above my SA limit. Y cannot run a second.
Tried with combination a lot of VDD2 and everything, I cannot step through 1.23V.

 

[zebra_hun]

@ Darkthrone

In the case of 2x16Gb, Tx 1.17V, VDDQ 1.38V, VDD 1.44V should theoretically be enough.
In many cases, I see that people apply too much voltage, especially to the VDDQ/Tx pair.
For me, it moves together.
E.g.: Tx 1.175V ---> VDDQ 1.38V.
But Tx 1.20V ---> VDDQ 1.41V is also good.
~ 200mV Delta
VDD + 60mV to VDDQ

I have a friend with the same configuration as mine. (Apex and 2x16Gb a die) I usually send him the CMO file, and he also has a flawless Y Cruncher. I see that it is cpu instability, as Veii writes.
I have experienced this many times, that Y Cruncher runs for a relatively long time, but fails after many, many minutes. It's annoying I know.
Out of curiosity, I just did an hour of Y running with "warm" water, since it's an extreme summer here.
Also out of curiosity, I set everything back to AUTO, LLC, AC LL, etc., only the V/F curve is active.
During testing, I saw that the Ring Down bin should not have been set to AUTO, since in any case the Core Clock -600MHz is.
Don't matter, it was just a test.
8000 C36 46 16 46 58 480 must go with such voltages.

 

[Veii]

I don't think there are user errors in this case. For me TM5 freezes after some cycles when I am above my SA limit. Y cannot run a second.
Tried with combination a lot of VDD2 and everything, I cannot step through 1.23V.

Yea no i mean,
On such big ODT change a lot of options have to follow and correct.
We depend on ASUS-HQ to have some sort of lookup table build in
Because training can be good or bad, too much (on unstable state) training very much will be bad.

MVDD + 60mV to MVDDQ

60 is the minimum that it can work and will work
~105 is where you can see RTT issues
Now we sit near 150-200mV delta.

VDDQ_IMC never needed to go that high on low-imp ODT state (CPU)
Same for VDDIO (here its VDD2_CPU). Never needed to be high to begin with
Unless ODT is weak. Then voltages skyrocket and with high voltages , weaker ODTs need to follow (for all other parts)
That plus RTTs sitting only on DIMM ~ makes balancing complicated.

Else yes, absolutely.
Delta mostly depends on ODT state, and capacity of dimm basically implies weaker ODT state (on some of them)
Soo delta range changes by capacity. Now if that thing even can function depends on DIMM-Vendors PCB
If it needs stronger ODT, of course delta will shift a bit again.

I believe balance wasnt optimal in the early bioses.
But if user forces all, i see barely a change except due to ME-FW & CPU Curve.

 

[Darkthrone]

RTT_WR 48,
NOM both to 80,
RTT_PARK to 40,
PARK_DQS to 48

Do I have to disable Dimm RON Training also along with these?

 

[tibcsi0407]

Because training can be good or bad, too much (on unstable state) training very much will be bad.

Actually I remember that with my 13900KS somehow I was able to run it on 1.35V SA, and it was stable. And after a BIOS reset I wasn't to able to make it work again.
Maybe that came from an ODT training "issue".

 

[Veii]

During testing, I saw that the Ring Down bin should not have been set to AUTO, since in any case the Core Clock -600MHz is.

Ring + UCLK (MCLK rather i think), + X making QCLK
Doesnt need to be the same value as Frontend P-Core Clk

Both are connected PCLK & RingCLK
But they are not the exact same frequency and are different IP Blocks.
Downbin guarantees that dynamicness remains and CPU doesnt pump clock when it doesnt need to
And also causes no scenario where Clk is higher than available distributed voltage (VID) = crash or CEP captured

^ especially causes no scenario that will eat into tight powerbudget. Because frontend clock is irrelevant.
But its just part of it. We should be using SA_GV too. Tho may cause bad frametime or be badly configured by Intel-HQ for desktop.
I remember ADL++ had Ring stability issues. Likely it continues to exist in some way or form. Especially when we overclock things.

Do I have to disable Dimm RON Training also along with these?

RON are the

which is 1DPC exclusive and only good new PCB - else its 40-34, 34-40
As those RONs are very weak.

But its RTTs Training
You dont need to , if you force all.

Auto = train remain undefined values, if lookuptable has no entry
Enabled = Train values, ignore lookup table
Disabled = check lookup table, else default to default, if both miss dont train at all. (no boot)

Beitrag automatisch zusammengeführt: 29.05.2024

Ring + UCLK (MCLK rather i think), + X making QCLK

Can be tested if MCLK or UCLK, if G4 vs G2 can sustain identical RingCLK.
Or ringCLK needs to be much lower for G4 sustainability.

 

[Darkthrone]

But its RTTs Training
You dont need to , if you force all.

I made a silly mistake, i had VDDQ training at Auto before, so i dont know if that is a problem.
Changed it to Disbled along with the RTTs now.
Other than that i have no issue with these RTTs to boot and run ycruncher although i have a drop in speed on both VST/VT3

Running TM5 Usmus now and report back...

 

[Veii]

I made a silly mistake, i had VDDQ training at Auto before, so i dont know if that is a problem.
Changed it to Disabled along with the RTTs now.

It was the reason you were never voltage stable to begin with
Interesting about the speed drop.
It has no need to do that unless you are actively hitting a power limiter.
// Aware it will lower both IVRs due to hitting powerlimiters

Ah thats resolvable.
Yes very interesting that IVR VDDQ_IMC would correct downwards and train downwards
But fully hold its state without any variance with training disabled.

Learned something new~

Beitrag automatisch zusammengeführt: 29.05.2024

Thats the WorkTool generated V/F right ?
How many V/F points did you use there ~ do you remember ?
EDIT:

It was the reason you were never voltage stable to begin with
Interesting about the speed drop.

In such case, we/i maybe didnt nail the IVR VDDQ_IMC voltage & 55min wasnt enough to show its not perfect.
I wonder what limiter you hit.
Ring doesnt boost up.

VR-MAX is on 1500, 1550 or 1600 ?

 

[alberts2]

Since last time we checked i reinstalled the original ILM, i couldnt make TR contact frame to work correctly. Everyone say if you screw it down fully it works perfect but that was not the case with me.

The instructions to tighten the screws of the contact frames all the way are just wrong. If you follow that your success is dependent on the tolerances of the contact frame and those of the cheap plastic socket. Additionally there's different manufacturers and versions of the LGA1700 socket being used. These probably aren't 100% identically to each other.

Just look at the trouble Thermal Grizzly has with it's direct die cooling solutions. They relied on the plastic being the same but it seems that's not the case.

 

[Darkthrone]

Ring doesnt boost up.

VR-MAX is on 1500, 1550 or 1600 ?

Ring is set to Auto/42 so not to boost to default 50. Do you want to change it?
VR Max is at 1550

Here is my TM5

 

[tibcsi0407]

Do you want to try and insta crash the system with:

SA 1300mV
VDD2_CPU 1400mV (if no boot 1380)
VDDQ_IMC 1335 (else 1330)

It ran for 2 minutes in VST, then it dropped it. But not with error, it just stopped and package power went idle.
But it wasn't insta crash.

 

[Veii]

Just look at the trouble Thermal Grizzly has with it's direct die cooling solutions. They relied on the plastic being the same but it seems that's not the case.

Hey hey
Do you mean the trouble on Romans Frame or the instability with the Mycro Copper Block at first ?
Just watched

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Yes, he makes now basically everything right. Tolerances are fine. Awareness of Metalic above the trace (gap) is fine.

His problem mostly come from wanting too much perfectionism
And with low tolerance, those "little" issues start to appear very significantly

I hope he see's my comment.

It ran for 2 minutes in VST, then it dropped it. But not with error, it just stopped and package power went idle.
But it wasn't insta crash.

mmmmm

Another test please, this time with 120mV gap inside mem (1680-1560)
And 1470 IVR VDDQ_IMC

If longer/faster, let me know
if no boot ~ then we have to fall back to own RTTs.

Ring is set to Auto/42 so not to boost to default 50. Do you want to change it?
VR Max is at 1550

Ahh
Both ok, i see
VR MAX you can go to 1600 ~ you got a KS
Ring you can keep on Auto

We dont want downgraded clock causing it to not fully load it
We want full load to find issues that dont appear instantly.

 

[Darkthrone]

VR MAX you can go to 1600
Ring you can keep on Auto

We dont want downgraded clock causing it to not fully load it
We want full load to find issues that don’t appear instantly.

Ok I will change those two
Can I go with PL1/PL2 253/320 for testing purposes or keep both at 320?

So what we do next?

 

[Veii]

Ok I will change those two
Can I go with PL1/PL2 253/320 for testing purposes or keep both at 320?

So what we do next?

Powerprofile depends on you
320-320 is odd.
But PL1/2 limiters generally can ruin memOC, because of low margins that get even lower when things start to downclock (irregularly)

Depends how busy you are.
I would not use HT-Off, ever

It might work as bandaid, but too many bandaids = no peak clock by more struggle in not seeing actual issue.

If you're not busy, see when you fail y-cruncher with HT-Off on 7800.
Set looks ok tbh.

You can use this tool for now

Releases · mann1x/CPUDoc

Contribute to mann1x/CPUDoc development by creating an account on GitHub.

github.com

https://mega.nz/file/pm4GASTT#t_op3o1woHhKIOCC7YcszxpwX7EhQFN327yEU5glNl4 Dev branch but has Monitor-DPI scaling issues.
It has support from i7-970 (2010) to todays CPUs.

To manage HT slowdown, scheduler and save a bit of power
InpoutX64 can go if you really want, as that is Zen focused.

EDIT:
Just dont use it on CPU/MemBenchmarks ~ because it pools quite fast.
For gaming, GPU XOC and other normal usage, its great~~
Powerplan for Intel is not too bad, but i can't vouch for it yet.
I have a better idea for this, but dont feel like working on it right now.
Windows thread sceduler especially 23h2++ should be fine for this + some polite asking by the tool.

 

[tibcsi0407]

Another test please, this time with 120mV gap inside mem (1680-1560)
And 1470 IVR VDDQ_IMC

If longer/faster, let me know
if no boot ~ then we have to fall back to own RTTs.

Will do it soon. Tried my configuration after retraining.
Now set ICCMAX to 400A and VRMAX to 1600. Even with this setting TVB kicks in and getting very good bitrates.
Something crashing in the background with my EC sometimes. Qled jumps to 01 and look at the motherboard and CPU temps in Hwinfo. It's funny. This happens with my freshly installed Windows, never happened before. Could be an ACPI issue, but I have no idea what.
I have fan control in the background

 

[Veii]

Will do it soon. Tried my configuration after retraining.
Now set ICCMAX to 400A and VRMAX to 1600. Even with this setting TVB kicks in and getting very good bitrates.

Someday we gonna see 8600 from you. Hopefully then 8800 too.
But 8600 at least so i can sleep better

Once 8600 is done, 10400 or 12000MT/s G4, would be fun for you to run~
Because at this point why not. 10K strap is so so, but 10400MT/s is doable.
Else 9600 MT/s it is ~ but that could be equal or slower than 8600 G2

 

[tibcsi0407]

Someday we gonna see 8600 from you. Hopefully then 8800 too.
But 8600 at least so i can sleep better

Maybe with the new P122 CPU of I get it. It is MC SP 91 and 1,488V Vid at 62X.

Do you have any idea for my Qled issue?

 

[Veii]

Do you have any idea for my Qled issue?

I need to checkk, sorry i missed it
Users having 01h debug code ?

G4 is not that hard as it sounds.
We all struggle with CPU/Ring issues mostly. Its not an MCLK issue.
Mem can be pushed if you know what you do.
This gen Hynix can take it.

 

[Darkthrone]

Powerprofile depends on you
320-320 is odd.
But PL1/2 limiters generally can ruin memOC, because of low margins that get even lower when things start to downclock (irregularly)

Depends how busy you are.
I would not use HT-Off, ever

It might work as a bandaid, but too many bandaids = no peak clock by more struggle in not seeing an actual issue.

If you're not busy, see when you fail y-cruncher with HT-Off on 7800.
Set looks ok tbh.

You can use this tool for now

Releases · mann1x/CPUDoc

Contribute to mann1x/CPUDoc development by creating an account on GitHub.

github.com

https://mega.nz/file/pm4GASTT#t_op3o1woHhKIOCC7YcszxpwX7EhQFN327yEU5glNl4 Dev branch but has Monitor-DPI scaling issues.
It has support from i7-970 (2010) to todays CPUs.
Anhang anzeigen 1002146
To manage HT slowdown, scheduler and save a bit of power
InpoutX64 can go if you really want, as that is Zen focused.

So better to have CPU Current Limit Max to 400A and leave PL1/PL2 at Auto?

Run ycruncher infinitely/for hours at 7800?
Isn't it better to start trying 8000?

Does this program need setup or i just run it at default settings?

 

[tibcsi0407]

I need to checkk, sorry i missed it
Users having 01h debug code ?

It just jumps to 01, maybe it is because it measures 101C on CPU for some reason.

The new setting failed:

 

[Veii]

So better to have CPU Current Limit Max to 400A and leave PL1/PL2 at Auto?

I think ICCMAX + VRMAX together are enough to protect the sample
PL1/2 is for fashion usage and as powersupply limiter.
Unfortunately tech-media hasnt catched it yet.

ICCMAX and PPP+PL4 can react nearly instantly,
PL1/2 is slow. Very slow. Cpu would be dead by their own voltage spikes, if both above wouldnt exist.

Does this program need setup or i just run it at default settings?

You can by default disable or enable some things , like powerplan behavior and gamemode awareness isnt really needed
Zen stuff for the inpout driver is not needed either and will conflict with other sensor programs or anticheats.

Else start, get it to run (needs microsoft dll's)
And thats all, you can see if you like its behavior. It does auto-configure.
Shouldnt be heavier than taskmanager, and bit lighter than hwinfo.

Run ycruncher infinitely/for hours at 7800?
Isn't it better to start trying 8000?

7800 with HT (normal operation), is the target to have a foundation.
From that foundation later you scale up.
Voltages are easy to mess with if you have something to fallback to.
I remember you had nothing that can be called stable.

So far all looks fine
But yes let cpu boost and behave how you bought it
Auto ring, auto LLC.

Beitrag automatisch zusammengeführt: 29.05.2024

It just jumps to 01, maybe it is because it measures 101C on CPU for some reason.

The new setting failed:

SA idle 1.28v
SA VID 1.305v

mm mm it really doesnt like it
we can postpone that fun when more values are force-set

Soo what prevents you currently on 8533 again ?
Or you wanted that CL32

It just jumps to 01, maybe it is because it measures 101C on CPU for some reason.

Sorry i dont know
if its displaying the CPU temp, it would fluctuate.
101-105 is fine for 14th gen onwards (depends on sensor)

Debug-Code wouldnt lock itself to a temp value.
EDIT:
Debug code would go from 99 to 65h then ~ for 101 decimal
Maybe tho, maybe (x1) (01) - would be 101. But i dont know.

 

[alberts2]

His problem mostly come from wanting too much perfectionism
And with low tolerance, those "little" issues start to appear very significantly

His way of dealing with this issue is excellent and on the technical side it's a learning opportunity.

Relying on the dimensions of the plastic socket to get a perfect amount of mounting pressure while also having perfekt contact between the cpu die and cooler was probably a mistake. Multiple suppliers manufacture these sockets and even slight differences can lead to problems. If the plastic is higher on some sockets than you can end up with a gap between the die and cooler. This would explain the higher temperatures.

The screws of the contact frames should ideally be tightened using a torque wrench or screwdriver. Similarly to the mounting process for the LGA4677 Cpu's or AMD's server Cpu's. For LGA4677 the torque is 0.6NM or 5.3 inch pounds. But no idea what the ideal torque for these LGA1700 contact frames would be.

 

[Veii]

Yes

Relying on the dimensions of the plastic socket to get a perfect amount of mounting pressure while also having perfekt contact between the cpu die and cooler was probably a mistake.

Was due to not being aware and maybe also wrongly educated about electricity.
He got to it, but phrased it in german of not being sure why it is a thing, yet it being a thing.

He can work around that.

The tolerance issues are annoying.
Yes having scenarios (reading) that sometimes the socket frame is higher than the substrate's crystal
Was even for me, beyond strange.
To have such big tolerances there too, but i guess its normal when it becomes a low priority piece.

Honestly, me personally it doesn't even wonder.
It's the same topic i've been gospelling around for months now.
"Liquid TIM over 150 microns is a trouble. Unusable above 200 microns"
Now if that 150-200 microns cap in his good manufacturing turns to 350-400 microns. Forget any liquid-tim.

I'm not even close to surprised
But its odd to see that socket covers have different heights.
One can hope that socket-springs at least define to tight tolerances and the PCB is a better way to handle this

IMO he doesnt even need to fully cover the traces.
Go like AMD and make feets. Leave an airgap above them if you can not fill this space with non-inductive material.

0.6Nm doesnt work everywhere tho. Ppl in medical-tech industry (motorized hands) need to work with .3 and .4Nm
They got 3-4 different sizes for different type of screws. (aware of a close-worker there, visiting them here and there, its fascinating)
The CPU doesnt really move around and springs already supply a counter force.

To throw one more fun variable, not every crystal is the same height, hence Nm pressure will differ.
People just need to use Fujifilm Prescale LLLW ~ for direct-die fun . Like he does.
Imagine supplying lets say 1Nm of force just to tiny corner pieces of the crystal vs to the whole crystal. Of course it will crack.

 

[tibcsi0407]

Soo what prevents you currently on 8533 again ?

Working on it right now, haha. On C34, if it can handle it.
I will put back my Xtreems and check it with those too. I tried that kit only with the KS.

if its displaying the CPU temp, it would fluctuate.
101-105 is fine for 14th gen onwards (depends on sensor)

It shows the package temp actually which is much lower.


Edit

8533C34 wants too much Voltage, it doesn't worth it to go above 1.70V VDD.

 

[Darkthrone]

I think ICCMAX + VRMAX together are enough to protect the sample

ICCMAX 400
VRMAX 1600
PL1 Auto
PL2 Auto
LLC Auto
Ring Auto
55/42 HT On

VST fail immediately while VT3 seem to run...any ideas?
But i cant let it run close to 100c for hours sadly...

 

[tibcsi0407]

ICCMAX 400
VRMAX 1600
PL1 Auto
PL2 Auto
LLC Auto
Ring Auto
55/42 HT On

VST fail immediately while VT3 seem to run...any ideas?
But i cant let it run close to 100c for hours sadly...

Anhang anzeigen 1002187

Why that much Vcore on 5500?