@Veii hello again, while starting ram OC can you give me some pointers to.keep in mind, is SA and CPU tx related? If so what's the delta or range I should set them. And mem vdd/vddq delay I saw your post months ago saying mem delta depends on tx or SA I can't remember. Anyway can you explain what the procODT does and how I could get the so called amperage in links to match. I have good stability at 8200, with SA 1.12 vddq training on and tx1.2-1.24 mc1.3-1.32 and dimms 1.55/1.4 but once I try 8400 just 1 bin higher my vt3 doesn't even start. I'm starting to think my motherboard might be the limitation rather than dimms or CPU because I've already had multiple CPUs and ram sticks but just one apex encore. I do have retrain issues but once stable it's stable even after coldboot, unless I change something in bios and undo the change after which even the initially"stable" config dies. Currently I am at 8000 36-48-48-64 with ctlvrefup 141. sA 1.12 mc 1.32 tx 1.24 and dimms 1.54/1.4
[Sammelthread] Intel DDR5 RAM OC Thread
- Ersteller even.de
- Erstellt am
zebra_hun
Profi
Heute habe ich die Speicher-Timings etwas enger gemacht. Nach dem TM5-Test habe ich die Kühlung umgebaut, Y Cruncher lief bereits gekühlt.
25 Cycle TM5
90 Minutes VST/VT3
Tx (VDDQ_CPU) 1.25V
IMC (VDD2) 1.35V (1.31V Drop)
VCC SA (VDD_CPU) 1.12V
VDD_Mem 1.47V
VDDQ_Mem 1.44V
AC LL 0.25
DC LL AUTO
CEP Disabled
tXSR 519
tXP 30
tPPD 2
tCPDED 20
tPRPDEN 2
tRDPDEN 47
ATC falsch Werten:
tWTR_L 16 --->tWRRD_sg auto
tWTR_S 4 --->tWRRD_dg auto
**************
Ctl0 dqvrefup [170]
Ctl0 dqvrefdn [88]
DQ RTT WR [40 DRAM Clock]
DQ RTT NOM RD [40 DRAM Clock]
DQ RTT NOM WR [34 DRAM Clock]
DQ RTT PARK [34 DRAM Clock]
DQ RTT PARK DQS [34 DRAM Clock]
GroupA CA ODT [240 DRAM Clock]
GroupA CS ODT [0 DRAM Clock]
GroupA CK ODT [0 DRAM Clock]
GroupB CA ODT [60 DRAM Clock]
GroupB CS ODT [40 DRAM Clock]
GroupB CK ODT [40 DRAM Clock]
Pull-up Output Driver Impedance [48 DRAM Clock]
Pull-Down Output Driver Impedance [40 DRAM Clock]
DQ RTT WR [40 DRAM Clock]
DQ RTT NOM RD [40 DRAM Clock]
DQ RTT NOM WR [34 DRAM Clock]
DQ RTT PARK [34 DRAM Clock]
DQ RTT PARK DQS [34 DRAM Clock]
GroupA CA ODT [240 DRAM Clock]
GroupA CS ODT [0 DRAM Clock]
GroupA CK ODT [0 DRAM Clock]
GroupB CA ODT [60 DRAM Clock]
GroupB CS ODT [40 DRAM Clock]
GroupB CK ODT [40 DRAM Clock]
Pull-up Output Driver Impedance [40 DRAM Clock]
Pull-Down Output Driver Impedance [48 DRAM Clock]
Damals ich habe das gesagt, 7200 Y stable unglaublich. Geschaft.
7600 war gleiche, viele Hilfe von Veii, ging.
8000C36 war in meinem Augen auch "impossible", aber jetzt geht's.
Training oder cold boot Probleme habe ich keine, ganze RTTs, ODTs manuel sind.
Drei Stunden lang sind Y gegangen, dann VT3 Y Error
Naja, es ist super schon mir.
Danke schön Veii
25 Cycle TM5
90 Minutes VST/VT3
Tx (VDDQ_CPU) 1.25V
IMC (VDD2) 1.35V (1.31V Drop)
VCC SA (VDD_CPU) 1.12V
VDD_Mem 1.47V
VDDQ_Mem 1.44V
AC LL 0.25
DC LL AUTO
CEP Disabled
tXSR 519
tXP 30
tPPD 2
tCPDED 20
tPRPDEN 2
tRDPDEN 47
ATC falsch Werten:
tWTR_L 16 --->tWRRD_sg auto
tWTR_S 4 --->tWRRD_dg auto
**************
Ctl0 dqvrefup [170]
Ctl0 dqvrefdn [88]
DQ RTT WR [40 DRAM Clock]
DQ RTT NOM RD [40 DRAM Clock]
DQ RTT NOM WR [34 DRAM Clock]
DQ RTT PARK [34 DRAM Clock]
DQ RTT PARK DQS [34 DRAM Clock]
GroupA CA ODT [240 DRAM Clock]
GroupA CS ODT [0 DRAM Clock]
GroupA CK ODT [0 DRAM Clock]
GroupB CA ODT [60 DRAM Clock]
GroupB CS ODT [40 DRAM Clock]
GroupB CK ODT [40 DRAM Clock]
Pull-up Output Driver Impedance [48 DRAM Clock]
Pull-Down Output Driver Impedance [40 DRAM Clock]
DQ RTT WR [40 DRAM Clock]
DQ RTT NOM RD [40 DRAM Clock]
DQ RTT NOM WR [34 DRAM Clock]
DQ RTT PARK [34 DRAM Clock]
DQ RTT PARK DQS [34 DRAM Clock]
GroupA CA ODT [240 DRAM Clock]
GroupA CS ODT [0 DRAM Clock]
GroupA CK ODT [0 DRAM Clock]
GroupB CA ODT [60 DRAM Clock]
GroupB CS ODT [40 DRAM Clock]
GroupB CK ODT [40 DRAM Clock]
Pull-up Output Driver Impedance [40 DRAM Clock]
Pull-Down Output Driver Impedance [48 DRAM Clock]
Damals ich habe das gesagt, 7200 Y stable unglaublich. Geschaft.
7600 war gleiche, viele Hilfe von Veii, ging.
8000C36 war in meinem Augen auch "impossible", aber jetzt geht's.
Training oder cold boot Probleme habe ich keine, ganze RTTs, ODTs manuel sind.
Drei Stunden lang sind Y gegangen, dann VT3 Y Error
Naja, es ist super schon mir.
Danke schön Veii
Anhänge
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This is the issue.
CTL1's depend on ODT & RTT fully.
They have capacity influence, as side issue - but its rather due to RTTs changing.
Don't use only one CTL1. I've done mistakes, but those are at this point 5? 6 months old with correction posts.
Maybe it was missed on couple of places, i'm sorry.
The questions you ask, are answered here 3 times already.
Lets repeat them another day.
SA and so VDD2 starting point depends on your V/F curve (VID max) , how leaky sample is.
It is not readable if its higher VID due to lack of 105° stability (on 14th gen) or its because substrate is leaky.
But higher VID , higher voltages required.
Found ~ 1.46 VID
Please add some basic description of your setup in your , biography ?
Signature is the word.
Ok found on your first post, you are on 2x24gb
~150mV delta was it for 24gb,
Give:
SA 1.145
VDD2_CPU 1400
VDDQ_CPU 1340
VDD_MEM 1550
VDDQ_MEM 1490
A try.
VDDQ Training off ! & MRC Fastboot off + Fastboot Off
// after applying the settings, PSU off, press the power button to discharge and then try to post
3 cycles y-cruncher VST+VT3 or N63+VT3 (to sanity check for CPU errors that will mess with TM5) then TM5.
If you instant error (which might be happening) ~ play with (IVR) VDDQ_CPU +/- 5 mV.
^ it is likely between 120-160mV for this setup.
// If you refuse to post, lower in 10mV steps (more delta) till you can post. Leave mem alone. Don't use any CTL's.
For good CPU health,
VRMAX 1550mV & 346A ICCMAX
If you have exceptional cooling, you can go 400A on ICCMAX.
Open PT1/PT2 limiters. 95° all core, 105° burst (per core) thermal limit.
Without messing with CPU curve, ICCMAX will trigger and throttle.
Remove any IA_DC Loadline.
We target 90+ minutes y-cruncher (both tests alternating) and 25 cycles TM5 1usmus_v3.
You'll found later one last pages here. The updated version.
105° pearks are ok, 95° whole chip is ok for 14th gen ~ 110-115° spikes are not ! Keep an eye on y-cruncher.
At 110° under this load amount, it will hurt it - slowly but surely.
If you want to hurt your poor chip, 120° at this load will speed up degradation.
Please don't let it ever request beyond 1.55 VID and never reach 110° spikes at such loads.
Those are silly targets, but thermal throttle system has to be functional and keep CPU stable.
Do NOT use any fixed core clock or fixed core voltages on those limits !
Generally do not run y-cruncher like loads at fixed clock or fixed voltage. Any;
Beitrag automatisch zusammengeführt:
Every time you change VID_SA, you need a cold boot. PSU OFF & verify SA VID applies with HWInfo.
Every time you switch off a training option (first time), you need a PSU OFF boot.
Beitrag automatisch zusammengeführt:
Versuche:
VDDQ_MEM 1400mV
VDDQ_CPU 1210mV
Sollte es nach 3h wieder errorn, mehr delta.
Du bist auf 190mV momentan. Hoch zu 200-225mV
180mV ist für 2 DPC., 16gb.
Bewege dich in 5mV schritten.
Ich möchte 6h Stabilität dass man sagen kann "alles ist perfekt", aber 90min+ sind erstmal genug.
Sobald du 6h schaffst, kannst du beginnen CTL1's rauszusuchen
2-3h korrigieren kann es. 6h absolut nicht
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Ok so I'm not on mdie anymore. I have 2x16 Adie 6000c30 teamgroup. Are the dimm voltage still the same? Also my timings are 8000 36-48-48-60 rn it's 1.53/1.4.This is the issue.
CTL1's depend on ODT & RTT fully.
They have capacity influence, as side issue - but its rather due to RTTs changing.
Don't use only one CTL1. I've done mistakes, but those are at this point 5? 6 months old with correction posts.
Maybe it was missed on couple of places, i'm sorry.
The questions you ask, are answered here 3 times already.
Lets repeat them another day.
SA and so VDD2 starting point depends on your V/F curve (VID max) , how leaky sample is.
It is not readable if its higher VID due to lack of 105° stability (on 14th gen) or its because substrate is leaky.
But higher VID , higher voltages required.
Found ~ 1.46 VID
Please add some basic description of your setup in your , biography ?
Signature is the word.
Ok found on your first post, you are on 2x24gb
~150mV delta was it for 24gb,
Give:
SA 1.145
VDD2_CPU 1400
VDDQ_CPU 1340
VDD_MEM 1550
VDDQ_MEM 1490
A try.
VDDQ Training off ! & MRC Fastboot off + Fastboot Off
// after applying the settings, PSU off, press the power button to discharge and then try to post
3 cycles y-cruncher VST+VT3 or N63+VT3 (to sanity check for CPU errors that will mess with TM5) then TM5.
If you instant error (which might be happening) ~ play with (IVR) VDDQ_CPU +/- 5 mV.
^ it is likely between 120-160mV for this setup.
// If you refuse to post, lower in 10mV steps (more delta) till you can post. Leave mem alone. Don't use any CTL's.
For good CPU health,
VRMAX 1550mV & 346A ICCMAX
If you have exceptional cooling, you can go 400A on ICCMAX.
Open PT1/PT2 limiters. 95° all core, 105° burst (per core) thermal limit.
Without messing with CPU curve, ICCMAX will trigger and throttle.
Remove any IA_DC Loadline.
We target 90+ minutes y-cruncher (both tests alternating) and 25 cycles TM5 1usmus_v3.
You'll found later one last pages here. The updated version.
105° pearks are ok, 95° whole chip is ok for 14th gen ~ 110-115° spikes are not ! Keep an eye on y-cruncher.
At 110° under this load amount, it will hurt it - slowly but surely.
If you want to hurt your poor chip, 120° at this load will speed up degradation.
Please don't let it ever request beyond 1.55 VID and never reach 110° spikes at such loads.
Those are silly targets, but thermal throttle system has to be functional and keep CPU stable.
Do NOT use any fixed core clock or fixed core voltages on those limits !
Generally do not run y-cruncher like loads at fixed clock or fixed voltage. Any;
Beitrag automatisch zusammengeführt:
Every time you change VID_SA, you need a cold boot. PSU OFF & verify SA VID applies with HWInfo.
Every time you switch off a training option (first time), you need a PSU OFF boot.
Beitrag automatisch zusammengeführt:
Versuche:
VDDQ_MEM 1400mV
VDDQ_CPU 1210mV
Sollte es nach 3h wieder errorn, mehr delta.
Du bist auf 190mV momentan. Hoch zu 200-225mV
180mV ist für 2 DPC., 16gb.
Bewege dich in 5mV schritten.
Ich möchte 6h Stabilität dass man sagen kann "alles ist perfekt", aber 90min+ sind erstmal genug.
Sobald du 6h schaffst, kannst du beginnen CTL1's rauszusuchen
2-3h korrigieren kann es. 6h absolut nicht
Then its ~200mV delta.
1290 VDDQ_CPU
My CPU is running very low clockspeed under load and not able to hit 5.7 at all if use less than 400A, I'm on AIO cooling with Hyperthreading disabled.
Edit: this is with VF tuned
Clock strap change is a long topic
Clock frequency number is not so important.
I dont know how to help you further
Highest chance is to hit curve max, with 1550mV VRMAX limit
ICCMAX should not be hit under such condition.
Its there to prevent transient spikes & overvoltage spikes.
G'Morning~
So 1.29tx and 1.49memDQ vdd 1.54 at 8000 36-48-48
Insta BDOD, went up to tx1.31 vt3 fail. 1.32 tx also failed. How far should i keep increasing TX?
Decreasing. More delta.
PSU off is important, because ~10 values depend on VDDQ_CPU state.
You can revert at lower clock if needed, till you find your baseline. Without the usage of CTL1's.
Delta stays the same across, unless drastic limitations changes behavior (or throttle causes a loss of supply)
Okay so just to be clear you wanted me to start at 200mV gap and keep increasing the delta and further lower my tx? Also what's a solid core test as per you, and how long should I run the core test to confirm rock solid core stability.
zebra_hun
Profi
Wir werden es sehen. Früher habe ich es schon gemerkt, postet hier. Y Cruncher mehr stabieler, wenn ich weniger Spannungen eingebe.
Einziege Problem ist das, TM5 wird schlechter.
Ich nutze immer 30mV steps, es kann ATC, HWINFO richtig auslesen. 1.41, 1.44, 1.47, 1.50 usw.
Jetzt lauft mit 1.21V TX (VDDQ_CPU) und 1.41V VDDQ_Mem.
Gerade 80. Mins.
Diese Profil ist jetzt schärfer. Es ist nicht 544, 131071, 12/8, 24/8, sondern 480, 262143, 8/8, 16/4. Für TM5 wird es harder.
Status Update:
Über drei Stunden durch.
Anhänge
Zuletzt bearbeitet:
tibcsi0407
Semiprofi
@Veii
Seems like I was able to fix the MC SP issue.
I had an Arctic backplate protector installed to support the original backplate to do not fall when I unscrewed the Iceman block ( I remembered wrong about it had Alphacool installed). Which is good for Iceman block, but not good for original ILM and Supercool block. Due to the bending restriction.
So I removed the backplate, reseated the CPU and now the MC SP is 84-84-84-84-82 in a row. 😊
Let's see if my stability comes back!
Rearranged the tubing a little too.
So now the pump goes to the RAM, then the CPU and after the 140x60 radiator.
So I don't have the huge pressure on the memory slot.
Seems like I was able to fix the MC SP issue.
I had an Arctic backplate protector installed to support the original backplate to do not fall when I unscrewed the Iceman block ( I remembered wrong about it had Alphacool installed). Which is good for Iceman block, but not good for original ILM and Supercool block. Due to the bending restriction.
So I removed the backplate, reseated the CPU and now the MC SP is 84-84-84-84-82 in a row. 😊
Let's see if my stability comes back!
Rearranged the tubing a little too.
So now the pump goes to the RAM, then the CPU and after the 140x60 radiator.
So I don't have the huge pressure on the memory slot.
Zuletzt bearbeitet:
Maybe jump to this old post
And this one is a solid foundation
[Sammelthread] - Intel DDR5 RAM OC Thread
?:) Nope iot was 40/48 on both. Tried 40-34 34-40 on first slot
www.hardwareluxx.de
And this one
*Official* Intel DDR5 OC and 24/7 daily Memory Stability...
www.overclock.net
I think this way of hunting voltage can be ok
Tedious a bit, but Yuri's TM5 profile still goes strong.
Shouldnt take too long. TM5 hates signal dropouts, at least our profile.
Anta's profile is different. HCI is different.
I'm a bit worried on lack of information about your Cores/Curve OC topic.
Because cutting IA supply is not the way to go about this.
Soo maybe a biosprofile.txt dump is a good idea.
Else, delta's remain per board and per processor-ODT unique.
ProcODT here is automatic. Real IMC Voltage is automatic
You will have a harder time but it can be worked with. Everybody can too
I'm soo proud of madness's low voltage results.
He has an open mind and learned to integrate this minmaxing into his methods. Very happy;
Most bothersome may be how well ASUS Bioses can adapt. A positive and negative
Do cold boots please on SA or VDDQ_CPU changes. Far too much depends on both. They influence too many other values.
Beitrag automatisch zusammengeführt:
PMIC ist ein Troll
Schaue dir den oberen HWLUXX link an.
Input:
Actual targets
Das Board & PMIC trollt sehr gerne
PMIC kann sich selbst korrigieren.
Targets waren 1365mV VDDQ_MEM (180mV delta)
Wenn solch etwas passiert und es nicht "standartmäßig" droopy ist (wie manche Renesas)
Dann steuert das Board dagegen. Einfach Spannung richten und beobachten was das Board dir mitteilen möchte.
Spannungsschwankungen sind schlecht. 15mV im PMIC ist Erlaubt (VREF feature, hat +/- 15mV margins)
OC mode allerdings erlaubt nur 10mV anstelle -5, 5, +5 margins. Somit ist es -10, 10, +10 mV // aka wir bewegen uns in 30mV Schritten ab 1430mV (1425mV letztes 5mV non-OC mode registry)
Today is a good day, i see
Good timezone !Pleaase try to find time for sce tutorial. Its not hard;
I need somebody that tests and sanity checks some values for me. I don't trust a bios that i havent made
hahaI only trust one person , but FW team grew. Soo i trust nobody and like to sanitycheck.
Zuletzt bearbeitet:
tibcsi0407
Semiprofi
I will do that for sure, but I have some busy projects. I had to fix this issue because I need stability. 😊Today is a good day, I see
Please try to find time for sce tutorial. It's not hard;
I need someone who tests and sanity checks some values for me. I don't trust a bios that I haven't made
I only trust one person, but FW team grew. So I trust nobody and like to sanity check.
I also had to reduce VDD2 a little, maybe colder environment helps in that.
Y is still running now, only 6 minutes ago, but hey I wasn't able to run 5 seconds before, so it's a step forward. 😊
@Veii
Here's my exact settings in bios
Core clocks/Ring: all auto
VF offset page, 5.6 offset 80mV 5.8 20mV
That's all I did to core nothing else.
Ram
Mode: auto
Freq: 8000
Timings 8000 36-48-48-48-64 8/8/32 rrd/tfaw. 12 trtp
Trefi 65535, terts, 16/8 20/20 16/8 68/54
Voltages: 1.54/1.49(dimms DD/dq)
CPU SA 1.145 tx= testing around 1.29 range(200mV ddq delta), tx 1.28 no post, trying 1.27 now. mC voltage = 1.4 set
CPU power settings
Iccmax: 400A
PL: unlimited 4095W both pl1/2
Training: mrcFB,FB and vddq training all 3 are off👍.
Here's my exact settings in bios
Core clocks/Ring: all auto
VF offset page, 5.6 offset 80mV 5.8 20mV
That's all I did to core nothing else.
Ram
Mode: auto
Freq: 8000
Timings 8000 36-48-48-48-64 8/8/32 rrd/tfaw. 12 trtp
Trefi 65535, terts, 16/8 20/20 16/8 68/54
Voltages: 1.54/1.49(dimms DD/dq)
CPU SA 1.145 tx= testing around 1.29 range(200mV ddq delta), tx 1.28 no post, trying 1.27 now. mC voltage = 1.4 set
CPU power settings
Iccmax: 400A
PL: unlimited 4095W both pl1/2
Training: mrcFB,FB and vddq training all 3 are off👍.
Really not sure.
rODT is such complicated topic. There is zero information to work with;
And i cant just go and do 2-5mV testing myself, watching voltage behavior.
Got to work with what we have~
But no,
I don't think Intel would (bios) tune ODT based on thermals.
Because crystal is thermally stable. Like many times mentioned, it is very high thermal stable
Only near -50°C i expect some change. But that's cores side and not MC-Link. Both CPU side IVR will depend on Bios-ODT state. Barely on thermals.
Copper/Fiberglas is very stable too. You need way bellow -100°C to show some resistance changes in it (changes on the Mainboard).
I see i see
The mistake is that you didnt use ASUS Tool.exe to make the curve
P11 needs a smaller droop than P8-P10
Curve is logarithmic. The highest voltage point wins
If you have a situation where X voltage point is lower than the next one, this droop is completely ignored by the CPU.
Soo to have a log curve, you use his tool and offset by X amount
Values are delta's ontop of trained curve. You can not do "-50mV and expect -50mV linear drop"
This is not going to work.
This will happen many times.
Its normal because there is (little) parts that will correct.
If IVR VDDQ_CPU input is bad, or not within 15mV of "what could work" - it will not boot
Sadly sadly , apex boots too many things. It is difficult to nail the exact voltage now.
Generally hard mode, but you can do it
Try to find min and max delta of VDDQ<->VDDQ, that will not drop you a #0 on TM5
y-cruncher is important too, but to be somewhere in the ballpark , TM5 is a must.
Soo if 100mV and 230mV is what you get from your testing. Median (50%) is 165mV
75% is near 172mV but that cant work (165 or 180 are the closest steps)
We target 80-85% of it. Ah its just math and its early. My math could be wrong.
Just ~85% of your found min & max margins. Thats your VDDQ_CPU target.
tibcsi0407
Semiprofi
I don't know then, but I noticed in the last days when I investigated the issue, that I was able to run much lower VDD2 than before. Same for the TX.
Today I expreimented, I was able to run 30 minutes Y on CPU_VDDQ 1.18V with MVDDQ 1.47V.
RON is still 48-40-40-48.
Maybe it's due to the pressure, or the much colder mem. It's more than 10C colder now.
Anyway, it errored out after 12 minutes, so still need some adjustments, or fine tuning, I have no idea, but it's definitely a step forward now compared to the last days.
PMIC behaves, nice to see.
Maybe it was missed ~ i asked for a "currently changed" visual curve example
This may or may not adjust based on thermal headroom.
Sanity checking that part.
If you alternate SFT+FFT, can you get it to crash within 10min ? 5 loops // full capacity, no configs
Can you get it to crash on CB15 extreme (benchmate) ?
@Veii
So I have some questions
1: if I use Asus OC tool, should I undervolt the 6GHz VF point along with 5.6 and 5.8? I know I can't offset beyond lower VF point that's why I have 160mV headroom at 5.6 and 40mV at 5.8 point. For 6.0 it's 1.458V from 5.8 1.388 so a bigger gap
2: 1.25V tx and mddq1.49(240mV delta) is running vt3 now does this mean anything? Because 1.26,1.27,1.28,1.29 either failed post or vt3
3: which tm5 profile should I use for checking dq delta range? Is it 1usmus?
So I have some questions
1: if I use Asus OC tool, should I undervolt the 6GHz VF point along with 5.6 and 5.8? I know I can't offset beyond lower VF point that's why I have 160mV headroom at 5.6 and 40mV at 5.8 point. For 6.0 it's 1.458V from 5.8 1.388 so a bigger gap
2: 1.25V tx and mddq1.49(240mV delta) is running vt3 now does this mean anything? Because 1.26,1.27,1.28,1.29 either failed post or vt3
3: which tm5 profile should I use for checking dq delta range? Is it 1usmus?
Hmm where is that old writeup post. I'm not back home yet;
If you change lets say P11, it will shift all other necessary points under it too.
If you change afterwards P3, it will know what it changed, and calculate math further, shifting P3 and points under it to match a solid curve.
Now you can work against the tool and do big cuts or bumps. But its important to readout and see that there is no droopy spike
It will tell you exactly in 100MHz steps what voltage "most likely" is applied to curve. The targets it gives, then you enter in the Bios.
Now thats calculated curve and not VID or Vout.
Its a target. And if this target peaks too high (which it will do, it will calculate and extend higher if you run TVB for example)
Then if that hits VRMAX ceiling ,it will throttle.
CPU has own VID limits outside of what you can see. But you will notice this part by running raw compute tests and seeing that effective raw perf changes while effective "visual" core clock does not.
Inside the CPU there are many clocks, and all are load balanced.
It all spreads around in VID base, but we lack access to more parts - like Ring V/F. Tho ring clock strap depends on CPU clock strap #Loadbalanced
There are then guardbands too , and ya - big big topic
Basically use tool.exe to make the curve visually look pleasing, and analytically have no overlapping voltage conditions.
How big now steps between 100MHz have to be, shouldnt be your worry. Tool.exe dev is very talented and knows what he does, haha.
Well that it trained well.
But also that you are on the right path.
240mV is a bit over my notes , but bioses change ~ soo its expected
It has too many variables that mess with ODT, to exactly nail it.
But its close enough
If you change SA, your delta will change. Soo no touch on SA for now.
If you change SA, your VDD2 range and effectiveness will change too.
SA is very CPU leakage factor dependent. No touch~
EDIT:
If you have a low leakage godbin, we can go weak ODT, nearly no delta and high SA
But i prefer the opposite. Strong ODT, low voltages, and let the good board work for us.
This will not work on lower grade PCBs as its noise sensitive. But low voltages are always good, even if they kind of mean nothing on their own.
Strong CPU ODT & weak transmission lines (up to board) . Just my own approach on high thermals~~
Beitrag automatisch zusammengeführt:
TM5 coolCMD_1usmusV3_25.zip package
Newest TM5 plus updated 1usmus config.
Newest TM5 to utilize all cores and to properly load memory
Config change to properly load memory and to hopefully not, have win 11 issues on too little standby cache.
Ive shared it here around 6 times
2-3 times in the AMD thread, and on OCN it spreads slowly
If you cant find it, then somebody can repload
Zuletzt bearbeitet:
tibcsi0407
Semiprofi
@tibcsi0407 can you please share Asus OC tool and the tm5 coolCMD that veii is talking about.
Having a chiller is sooo pay 2 win, ahhh
Good results !
CB15 Extr is hard to run. Its very dynamic load at high VID. It runs because we are not silly and don't cut IA supply.
A bad curve or degraded CPU will simply not pass. Some come bad from the factory (partial fault is bios SVID, like 12% blame)
VT3 is also a dynamic VID jumping load.
Hmmmmm
Soo either ring or outside of it. I wonder
It most definitely is compute stable.
Chance to be SA related is very little too, maybe 18-20%.
Core related is <5% chance.
DQ/DQS related is 12% chance. Look at the powerdraw haha.
Well . . .
I know 133 strap is awkward to say the least. Very awkward decimal timings on DQ delays.
What happens if you go 8600 with this ?
Timings very likely are fine too. I think dimms can do this. VDDQ_MEM slight worry, but should be fine.
Yess it very much sounds ring related, but it can be also slopes.
Hard to say, it shouldnt be slopes. y-cruncher should error and such tests have to crash if DQs (cmd, ca, cs) are bad.
Step by step, test 8600 without changing anything at all (unless you run CTL0, then adjust, if not , no touch)
PSU off after strap change and lets see if it even posts
Make a profile please.
Later we'll try one more thing to isolate the issue.
Well 2 more different things.
EDIT:
We could go around this issue and shift slopes, but it bothers me that something little is not ok.
No going around the issue for now.
Oh, we dont utilize RX-DFE still, right ? You did listen to me that i want to only use it past 8600 ? Just checking
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zebra_hun
Profi
TM5 always with admin permissions, needed so windows doesnt do silly things.
Beitrag automatisch zusammengeführt:
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Top!
Hmmm,
Ich bin wirklich kein Fan von den RTTs haha.
Sie sind einfach nicht 70° mem stable. Bis etwa 48-52° schon.
Die sind für XOC.
8200MT/s erwartet dich - später mal. // VDD2 + 35-40mV muss genügen. Keine andere Änderung, außer vlt primaries langsamer (+2 CAS, +1 RCD, RAS fix, CWL fix).
Oder, du kannst beginnen CTL1 CmdVref UP für deine ODT+RTTs herauszufinden.
Zwischen 125-145 sollte es sein.
Wert 1,2,3 (innerhalb 3 Werte) wird booten. Sind einiges an restarts 🤭
Stabilität muss über 3h sein (slopes eigentlich ja 6h), aber wird auch in 10min failen bzw garnicht booten.
Achte auf die "raw compute" Werte, wenn du slopes änderst.
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zebra_hun
Profi
8200c36 48 18 48 60 544 gestern habe ich schon angefangen.
1.37500V VDD2 und 1.50/1.47V VDD/Q schon paar Runde TM5 gemacht.
Jetzt bin ich zurück auf 8000, schau mal moi.
Ich vertraue darauf, daß TM5 gehts gut wenn es schaft 6 Stunde
Garnichts ist sicher.
Heute habe ich frei, aber morgen muss ich schon in die Arbeit gehen.
Ich bin eine Schneke, ich weiss, sorry.
1.37500V VDD2 und 1.50/1.47V VDD/Q schon paar Runde TM5 gemacht.
Jetzt bin ich zurück auf 8000, schau mal moi.
Ich vertraue darauf, daß TM5 gehts gut wenn es schaft 6 Stunde
Garnichts ist sicher.
Heute habe ich frei, aber morgen muss ich schon in die Arbeit gehen.
Ich bin eine Schneke, ich weiss, sorry.
Mache dir keine SorgenIch vertraue darauf, daß TM5 gehts gut wenn es schaft 6 Stunde
Garnichts ist sicher.
Heute habe ich frei, aber morgen muss ich schon in die Arbeit gehen.
Ich bin eine Schneke, ich weiss, sorry.
Auszeit ist wichtig. memOC ist Mental stressig.
Wenn du die CTL1's für dein set herrausfindest, kann man für alle anderen Nutzer skallieren.
Jemand muss sie rausfinden, den ich kann nicht auf alten Ergebnissen hoffen. Zu viel hat sich geändert.
Ebenso waren es nicht meine. Hier arbeiten wir alle zusammen. Nichts privat.
Jede Person Hilft der anderen, damit Sachen weitergehen.
zebra_hun
Profi
Stress ist schon vorbei. Ich will schon keinen anderen cpu kaufen. Es ist mir gut
Sehr ruhiger Job habe ich jetzt, als Test lauft.
Draußen in Garten. Ich hab viele Baume, und die neue "Hände" muss ich abzwicken.
Ich weiss nicht, wie nennt diese Job.
Diese Forum ist sehr gut mich die Sprache üben
Lange Zeit habe ich DE nicht benutzt.
Katastrophe, ich weiss, aber hoffentlich, nicht so schwer mein Text verstehen.
4 Stunden
Sehr ruhiger Job habe ich jetzt, als Test lauft.
Draußen in Garten. Ich hab viele Baume, und die neue "Hände" muss ich abzwicken.
Ich weiss nicht, wie nennt diese Job.
Diese Forum ist sehr gut mich die Sprache üben
Lange Zeit habe ich DE nicht benutzt.
Katastrophe, ich weiss, aber hoffentlich, nicht so schwer mein Text verstehen.
4 Stunden
Anhänge
Klingt gutDer Stress ist schon vorbei. Ich will schon keine anderen CPU mehr kaufen. Eine ist mir gut
Ein sehr ruhigen Job habe ich jetzt, wärend der Test läuft.
Draußen in Garten. Ich habe viele Bäume, und die neuen "Hände" muss ich abzwicken.
Ich weiss nicht, wie man diesen Job nennt.
Dieses Forum ist sehr gut für mich, um die Sprache zu üben
Lange Zeit habe ich kein DE mehr benutzt.
Katastrophe, ich weiß, aber hoffentlich ist es nicht so schwer mein Text zu verstehen.
4 Stunden
Grammatik und Artikel, aber es macht Sinn und ist verständlich.
Ich hab, ich habe viele (mehrzahl die Bäume)
Der Job (dieser Job)
Das Forum (dieses)
Die Sprache oder "meine" Sprache
Mein wienerisch-deutsch ist auch nicht besonders ... attraktiv
Irgendwo ist das (gaming) englisch angenehmer bzw besser, als mein 23 Jahre langes Deutsch. 🤭
Hochdeutsch schreibe ich nur bei E-Mails anderer Firmen bzw wenn jemand lästig sein möchte.
Ich mag es absolut nicht, soo passiv-aggressiv ~ aber nun ja, Alltagsdeutsch halt.
Ja,
Eine gute Zeit um das Haus sauber zu machen haha.
