[Sammelthread] Intel DDR5 RAM OC Thread

Veii schrieb:
Funny that slot B has lower bandwidth, slightly.
This sounds like a ring issue tbh. Can you export me the Bios config ?

Do you pass 2-3 rounds of CB15 Extreme (benchmate) ?
Without it crashing ?
Zum Vergrößern anklicken....
It can pass everything and CB15 Extreme no issues. I feed it with 1.1208-1.137v under load just for VST/VT3 while it only needs like 1.09-1.1v for 56/44/44

[2024/05/28 14:13:51]
Ai Overclock Tuner [XMP II]
XMP [DDR5-7200 34-42-42-84-2N-1.40V-1.40V]
BCLK Frequency [100.0000]
PCIE Frequency [100.0000]
Intel(R) Adaptive Boost Technology [Auto]
ASUS MultiCore Enhancement [Auto – Lets BIOS Optimize]
SVID Behavior [Auto]
BCLK Frequency : DRAM Frequency Ratio [Auto]
Memory Controller : DRAM Frequency Ratio [Auto]
DRAM Frequency [DDR5-8000MHz]
DIMM Flex [Disabled]
Performance Core Ratio [Sync All Cores]
ALL-Core Ratio Limit [56]
Performance Core0 Specific Ratio Limit [Auto]
Performance Core0 specific Voltage [Auto]
Performance Core1 Specific Ratio Limit [Auto]
Performance Core1 specific Voltage [Auto]
Performance Core2 Specific Ratio Limit [Auto]
Performance Core2 specific Voltage [Auto]
Performance Core3 Specific Ratio Limit [Auto]
Performance Core3 specific Voltage [Auto]
*Performance Core4 Specific Ratio Limit [Auto]
Performance Core4 specific Voltage [Auto]
*Performance Core5 Specific Ratio Limit [Auto]
Performance Core5 specific Voltage [Auto]
Performance Core6 Specific Ratio Limit [Auto]
Performance Core6 specific Voltage [Auto]
Performance Core7 Specific Ratio Limit [Auto]
Performance Core7 specific Voltage [Auto]
Efficient Core Ratio [Sync All Cores]
ALL-Core Ratio Limit [44]
Efficient Core Group0 Specific Ratio Limit [Auto]
Efficient Core Group0 specific Voltage [Auto]
Efficient Core Group1 Specific Ratio Limit [Auto]
Efficient Core Group1 specific Voltage [Auto]
Efficient Core Group2 Specific Ratio Limit [Auto]
Efficient Core Group2 specific Voltage [Auto]
Efficient Core Group3 Specific Ratio Limit [Auto]
Efficient Core Group3 specific Voltage [Auto]
AVX2 [Auto]
AVX2 Ratio Offset to per-core Ratio Limit [Auto]
AVX2 Voltage Guardband Scale Factor [Auto]
Maximus Tweak [Mode 2]
DRAM CAS# Latency [36]
DRAM RAS# to CAS# Delay Read [48]
DRAM RAS# to CAS# Delay Write [48]
DRAM RAS# PRE Time [48]
DRAM RAS# ACT Time [60]
DRAM Command Rate [2N]
DRAM RAS# to RAS# Delay L [10]
DRAM RAS# to RAS# Delay S [8]
DRAM REF Cycle Time 2 [512]
DRAM REF Cycle Time Same Bank [416]
DRAM Refresh Interval [65535]
DRAM WRITE Recovery Time [Auto]
DRAM READ to PRE Time [12]
DRAM FOUR ACT WIN Time [32]
DRAM WRITE to READ Delay L [Auto]
DRAM WRITE to READ Delay S [Auto]
DRAM CKE Minimum Pulse Width [20]
DRAM Write Latency [34]
Ctl0 dqvrefup [Auto]
Ctl0 dqvrefdn [Auto]
Ctl0 dqodtvrefup [Auto]
Ctl0 dqodtvrefdn [Auto]
Ctl1 cmdvrefup [Auto]
Ctl1 ctlvrefup [Auto]
Ctl1 clkvrefup [Auto]
Ctl1 ckecsvrefup [Auto]
Ctl2 cmdvrefdn [Auto]
Ctl2 ctlvrefdn [Auto]
Ctl2 clkvrefdn [Auto]
Read Equalization RxEq Start Sign [-]
Read Equalization RxEq Start [Auto]
Read Equalization RxEq Stop Sign [-]
Read Equalization RxEq Stop [Auto]
ODT_READ_DURATION [Auto]
ODT_READ_DELAY [Auto]
ODT_WRITE_DURATION [Auto]
ODT_WRITE_DELAY [Auto]
DQ RTT WR [Auto]
DQ RTT NOM RD [Auto]
DQ RTT NOM WR [Auto]
DQ RTT PARK [Auto]
DQ RTT PARK DQS [Auto]
GroupA CA ODT [Auto]
GroupA CS ODT [Auto]
GroupA CK ODT [Auto]
GroupB CA ODT [Auto]
GroupB CS ODT [Auto]
GroupB CK ODT [Auto]
Pull-up Output Driver Impedance [Auto]
Pull-Down Output Driver Impedance [Auto]
DQ RTT WR [Auto]
DQ RTT NOM RD [Auto]
DQ RTT NOM WR [Auto]
DQ RTT PARK [Auto]
DQ RTT PARK DQS [Auto]
GroupA CA ODT [Auto]
GroupA CS ODT [Auto]
GroupA CK ODT [Auto]
GroupB CA ODT [Auto]
GroupB CS ODT [Auto]
GroupB CK ODT [Auto]
Pull-up Output Driver Impedance [Auto]
Pull-Down Output Driver Impedance [Auto]
Round Trip Latency Init Value MC0 CHA [Auto]
Round Trip Latency Max Value MC0 CHA [Auto]
Round Trip Latency Offset Value Mode Sign MC0 CHA [-]
Round Trip Latency Offset Value MC0 CHA [Auto]
Round Trip Latency Init Value MC0 CHB [Auto]
Round Trip Latency Max Value MC0 CHB [Auto]
Round Trip Latency Offset Value Mode Sign MC0 CHB [-]
Round Trip Latency Offset Value MC0 CHB [Auto]
Round Trip Latency Init Value MC1 CHA [Auto]
Round Trip Latency Max Value MC1 CHA [Auto]
Round Trip Latency Offset Value Mode Sign MC1 CHA [-]
Round Trip Latency Offset Value MC1 CHA [Auto]
Round Trip Latency Init Value MC1 CHB [Auto]
Round Trip Latency Max Value MC1 CHB [Auto]
Round Trip Latency Offset Value Mode Sign MC1 CHB [-]
Round Trip Latency Offset Value MC1 CHB [Auto]
Round Trip Latency MC0 CHA R0 [Auto]
Round Trip Latency MC0 CHA R1 [Auto]
Round Trip Latency MC0 CHA R2 [0]
Round Trip Latency MC0 CHA R3 [0]
Round Trip Latency MC0 CHA R4 [0]
Round Trip Latency MC0 CHA R5 [0]
Round Trip Latency MC0 CHA R6 [0]
Round Trip Latency MC0 CHA R7 [0]
Round Trip Latency MC0 CHB R0 [Auto]
Round Trip Latency MC0 CHB R1 [Auto]
Round Trip Latency MC0 CHB R2 [0]
Round Trip Latency MC0 CHB R3 [0]
Round Trip Latency MC0 CHB R4 [0]
Round Trip Latency MC0 CHB R5 [0]
Round Trip Latency MC0 CHB R6 [0]
Round Trip Latency MC0 CHB R7 [0]
Round Trip Latency MC1 CHA R0 [Auto]
Round Trip Latency MC1 CHA R1 [Auto]
Round Trip Latency MC1 CHA R2 [0]
Round Trip Latency MC1 CHA R3 [0]
Round Trip Latency MC1 CHA R4 [0]
Round Trip Latency MC1 CHA R5 [0]
Round Trip Latency MC1 CHA R6 [0]
Round Trip Latency MC1 CHA R7 [0]
Round Trip Latency MC1 CHB R0 [Auto]
Round Trip Latency MC1 CHB R1 [Auto]
Round Trip Latency MC1 CHB R2 [0]
Round Trip Latency MC1 CHB R3 [0]
Round Trip Latency MC1 CHB R4 [0]
Round Trip Latency MC1 CHB R5 [0]
Round Trip Latency MC1 CHB R6 [0]
Round Trip Latency MC1 CHB R7 [0]
Early Command Training [Auto]
SenseAmp Offset Training [Auto]
Early ReadMPR Timing Centering 2D [Auto]
Read MPR Training [Auto]
Receive Enable Training [Auto]
Jedec Write Leveling [Auto]
Early Write Time Centering 2D [Auto]
Early Read Time Centering 2D [Auto]
Write Timing Centering 1D [Auto]
Write Voltage Centering 1D [Auto]
Read Timing Centering 1D [Auto]
Read Timing Centering with JR [Auto]
Dimm ODT Training* [Auto]
Max RTT_WR [ODT Off]
DIMM RON Training* [Auto]
Write Drive Strength/Equalization 2D* [Auto]
Write Slew Rate Training* [Auto]
Read ODT Training* [Auto]
Comp Optimization Training [Auto]
Read Equalization Training* [Auto]
Read Amplifier Training* [Auto]
Write Timing Centering 2D [Auto]
Read Timing Centering 2D [Auto]
Command Voltage Centering [Auto]
Early Command Voltage Centering [Auto]
Write Voltage Centering 2D [Auto]
Read Voltage Centering 2D [Auto]
Late Command Training [Auto]
Round Trip Latency [Auto]
Turn Around Timing Training [Auto]
CMD CTL CLK Slew Rate [Auto]
CMD/CTL DS & E 2D [Auto]
Read Voltage Centering 1D [Auto]
TxDqTCO Comp Training* [Auto]
ClkTCO Comp Training* [Auto]
TxDqsTCO Comp Training* [Auto]
VccDLL Bypass Training [Auto]
CMD/CTL Drive Strength Up/Dn 2D [Auto]
DIMM CA ODT Training [Auto]
PanicVttDnLp Training* [Auto]
Read Vref Decap Training* [Auto]
Vddq Training [Disabled]
Duty Cycle Correction Training [Auto]
Periodic DCC [Auto]
Rank Margin Tool Per Bit [Auto]
DIMM DFE Training [Auto]
EARLY DIMM DFE Training [Auto]
Tx Dqs Dcc Training [Auto]
DRAM DCA Training [Auto]
Write Driver Strength Training [Auto]
Rank Margin Tool [Auto]
Memory Test [Auto]
DIMM SPD Alias Test [Auto]
Receive Enable Centering 1D [Auto]
Retrain Margin Check [Auto]
Write Drive Strength Up/Dn independently [Auto]
LPDDR DqDqs Re-Training [Auto]
Margin Check Limit [Disabled]
tRDRD_sg_Training [Auto]
tRDRD_sg_Runtime [16]
tRDRD_dg_Training [Auto]
tRDRD_dg_Runtime [8]
tRDWR_sg [20]
tRDWR_dg [20]
tWRWR_sg [16]
tWRWR_dg [8]
tWRRD_sg [64]
tWRRD_dg [54]
tRDRD_dr [0]
tRDRD_dd [0]
tRDWR_dr [0]
tRDWR_dd [0]
tWRWR_dr [0]
tWRWR_dd [0]
tWRRD_dr [0]
tWRRD_dd [0]
tRPRE [Auto]
tWPRE [Auto]
tWPOST [Auto]
tWRPRE [65]
tPRPDEN [2]
tRDPDEN [45]
tWRPDEN [66]
tCPDED [20]
tREFIX9 [Auto]
Ref Interval [Auto]
tXPDLL [Auto]
tXP [30]
tPPD [2]
tCCD_L_tDLLK [Auto]
tZQCAL [Auto]
tZQCS [Auto]
OREF_RI [Auto]
Refresh Watermarks [High]
Refresh Hp Wm [Auto]
Refresh Panic Wm [Auto]
Refresh Abr Release [Auto]
tXSDLL [Auto]
tZQOPER [Auto]
tMOD [Auto]
CounttREFIWhileRefEn [Auto]
HPRefOnMRS [Auto]
SRX Ref Debits [Auto]
RAISE BLK WAIT [Auto]
Ref Stagger En [Auto]
Ref Stagger Mode [Auto]
Disable Stolen Refresh [Auto]
En Ref Type Display [Auto]
Trefipulse Stagger Disable [Auto]
tRPab ext [Auto]
derating ext [Auto]
Allow 2cyc B2B LPDDR [Auto]
tCSH [Auto]
tCSL [Auto]
powerdown Enable [Auto]
idle length [Auto]
raise cke after exit latency [Auto]
powerdown latency [Auto]
powerdown length [Auto]
selfrefresh latency [Auto]
selfrefresh length [Auto]
ckevalid length [Auto]
ckevalid enable [Auto]
idle enable [Auto]
selfrefresh enable [Auto]
Address mirror [Auto]
no gear4 param divide [Auto]
x8 device [Auto]
no gear2 param divide [Auto]
ddr 1dpc split ranks on subch [Auto]
write0 enable [Auto]
MultiCycCmd [Auto]
WCKDiffLowInIdle [Auto]
PBR Disable [Auto]
PBR OOO Dis [Auto]
PBR Disable on hot [Auto]
PBR Exit on Idle Cnt [Auto]
tXSR [519]
Dec tCWL [Auto]
Add tCWL [Auto]
Add 1Qclk delay [Auto]
MRC Fast Boot [Disabled]
MCH Full Check [Auto]
Mem Over Clock Fail Count [1]
Training Profile [Standard Profile]
RxDfe [Auto]
Mrc Training Loop Count [Auto]
DRAM CLK Period [Auto]
Dll_bwsel [Auto]
Controller 0, Channel 0 Control [Enabled]
Controller 0, Channel 1 Control [Enabled]
Controller 1, Channel 0 Control [Enabled]
Controller 1, Channel 1 Control [Enabled]
MC_Vref0 [Auto]
MC_Vref1 [Auto]
MC_Vref2 [Auto]
Fine Granularity Refresh mode [Auto]
SDRAM Density Per Die [Auto]
SDRAM Banks Per Bank Group [Auto]
SDRAM Bank Groups [Auto]
Dynamic Memory Boost [Disabled]
Realtime Memory Frequency [Disabled]
SA GV [Disabled]
Voltage Monitor [Die Sense]
VRM Initialization Check [Enabled]
CPU Input Voltage Load-line Calibration [Level 3]
CPU Load-line Calibration [Level 5]
Synch ACDC Loadline with VRM Loadline [Disabled]
CPU Current Capability [140%]
CPU Current Reporting [100%]
Core Voltage Suspension [Auto]
CPU VRM Switching Frequency [Manual]
Fixed CPU VRM Switching Frequency(KHz) [500]
CPU Power Duty Control [Extreme]
CPU Power Phase Control [Extreme]
CPU Power Thermal Control [125]
CPU Core/Cache Boot Voltage [Auto]
CPU Input Boot Voltage [Auto]
PLL Termination Boot Voltage [Auto]
CPU Standby Boot Voltage [Auto]
Memory Controller Boot Voltage [Auto]
CPU Core Auto Voltage Cap [Auto]
CPU Input Auto Voltage Cap [Auto]
Memory Controller Auto Voltage Cap [Auto]
Maximum CPU Core Temperature [Auto]
Fast Throttle Threshold [Auto]
Package Temperature Threshold [Auto]
Regulate Frequency by above Threshold [Auto]
IVR Transmitter VDDQ ICCMAX [15]
Unlimited ICCMAX [Disabled]
CPU Core/Cache Current Limit Max. [400.00]
Long Duration Package Power Limit [253]
Package Power Time Window [Auto]
Short Duration Package Power Limit [320]
Dual Tau Boost [Disabled]
IA AC Load Line [Auto]
IA DC Load Line [Auto]
IA CEP [Disabled]
SA CEP [Disabled]
IA SoC Iccmax Reactive Protector [Auto]
Inverse Temperature Dependency Throttle [Auto]
IA VR Voltage Limit [1550]
CPU SVID Support [Auto]
Cache Dynamic OC Switcher [Auto]
TVB Voltage Optimizations [Auto]
Enhanced TVB [Auto]
Overclocking TVB [Auto]
Overclocking TVB Global Temperature Offset Sign [+]
Overclocking TVB Global Temperature Offset Value [Auto]
Offset Mode Sign 1 [+]
V/F Point 1 Offset [Auto]
Offset Mode Sign 2 [+]
V/F Point 2 Offset [Auto]
Offset Mode Sign 3 [+]
V/F Point 3 Offset [Auto]
Offset Mode Sign 4 [+]
V/F Point 4 Offset [Auto]
Offset Mode Sign 5 [+]
V/F Point 5 Offset [Auto]
Offset Mode Sign 6 [+]
V/F Point 6 Offset [Auto]
Offset Mode Sign 7 [+]
V/F Point 7 Offset [Auto]
Offset Mode Sign 8 [+]
V/F Point 8 Offset [Auto]
Offset Mode Sign 9 [+]
V/F Point 9 Offset [Auto]
Offset Mode Sign 10 [+]
V/F Point 10 Offset [Auto]
Offset Mode Sign 11 [+]
V/F Point 11 Offset [Auto]
Initial BCLK Frequency [100.0000]
Runtime BCLK OC [Disabled]
BCLK Amplitude [900mV]
BCLK Slew Rate [Fast]
BCLK Spread Spectrum [Disabled]
Initial PCIE Frequency [Auto]
PCIE/DMI Amplitude [900mV]
PCIE/DMI Slew Rate [Fast]
PCIE/DMI Spread Spectrum [Disabled]
Cold Boot PCIE Frequency [Auto]
Realtime Memory Timing [Enabled]
SPD Write Disable [TRUE]
PVD Ratio Threshold [Auto]
SA PLL Frequency Override [Auto]
BCLK TSC HW Fixup [Enabled]
Core Ratio Extension Mode [Disabled]
FLL OC mode [Auto]
UnderVolt Protection [Disabled]
Switch Microcode [Current Microcode]
Xtreme Tweaking [Disabled]
Core PLL Voltage [Auto]
GT PLL Voltage [Auto]
Ring PLL Voltage [Auto]
System Agent PLL Voltage [Auto]
Memory Controller PLL Voltage [Auto]
Efficient-core PLL Voltage [Auto]
CPU 1.8V Small Rail [Auto]
PLL Termination Voltage [Auto]
CPU Standby Voltage [Auto]
PCH 1.05V Voltage [Auto]
PCH 0.82V Voltage [Auto]
CPU Input Voltage Reset Voltage [Auto]
Eventual CPU Input Voltage [Auto]
Eventual Memory Controller Voltage [Auto]
Package Temperature Threshold [Auto]
Regulate Frequency by above Threshold [Auto]
Cooler Efficiency Customize [Keep Training]
Cooler Re-evaluation Algorithm [Normal]
Optimism Scale [100]
Ring Down Bin [Auto]
Min. CPU Cache Ratio [44]
Max. CPU Cache Ratio [44]
BCLK Aware Adaptive Voltage [Auto]
Actual VRM Core Voltage [Auto]
Global Core SVID Voltage [Adaptive Mode]
- Offset Mode Sign [-]
- Additional Turbo Mode CPU Core Voltage [Auto]
- Offset Voltage [0.04000]
Cache SVID Voltage [Auto]
CPU L2 Voltage [Auto]
CPU System Agent Voltage [Manual Mode]
- CPU System Agent Voltage Override [1.20000]
CPU Input Voltage [Auto]
High DRAM Voltage Mode [Enabled]
DRAM VDD Voltage [1.45000]
DRAM VDDQ Voltage [1.40000]
IVR Transmitter VDDQ Voltage [1.30000]
Memory Controller Voltage [1.40000]
MC Voltage Calculation Voltage Base [Auto]
VDD Calculation Voltage Base [Auto]
PMIC Voltages [Sync All PMICs]
SPD HUB VLDO (1.8V) [Auto]
SPD HUB VDDIO (1.0V) [Auto]
DRAM VDD Voltage [1.45000]
DRAM VDDQ Voltage [1.40000]
DRAM VPP Voltage [1.80000]
DRAM VDD Switching Frequency [Auto]
DRAM VDDQ Switching Frequency [Auto]
DRAM VPP Switching Frequency [Auto]
DRAM Current Capability [Auto]
PCI Express Native Power Management [Disabled]
DMI Link ASPM Control [Disabled]
ASPM [Disabled]
L1 Substates [Disabled]
DMI ASPM [Disabled]
DMI Gen3 ASPM [Disabled]
PEG - ASPM [Disabled]
PCI Express Clock Gating [Enabled]
Hardware Prefetcher [Enabled]
Adjacent Cache Line Prefetch [Disabled]
Intel (VMX) Virtualization Technology [Disabled]
Per P-Core Control [Disabled]
Per E-Core Control [Disabled]
Active Performance Cores [All]
Active Efficient Cores [All]
Hyper-Threading [Disabled]
Total Memory Encryption [Disabled]
Legacy Game Compatibility Mode [Disabled]
Boot performance mode [Auto]
Intel(R) SpeedStep(tm) [Disabled]
Intel(R) Speed Shift Technology [Disabled]
Turbo Mode [Enabled]
Acoustic Noise Mitigation [Disabled]
CPU C-states [Enabled]
Enhanced C-states [Enabled]
Package C State Limit [C8]
Thermal Monitor [Enabled]
Dual Tau Boost [Disabled]
VT-d [Disabled]
Memory Remap [Enabled]
Enable VMD controller [Enabled]
Map PCIe Storage under VMD [Disabled]
Map SATA Controller under VMD [Disabled]
M.2_2 Link Speed [Auto]
PCIEX16(G5)_1 Link Speed [Auto]
M.2_1 Link Speed [Auto]
PCIEX4(G4)_1 Link Speed [Auto]
PCIEX4(G4)_2 Link Speed [Auto]
M.2_3 Link Speed [Auto]
DIMM.2_1 Link Speed [Auto]
DIMM.2_2 Link Speed [Auto]
SATA Controller(s) [Enabled]
Aggressive LPM Support [Disabled]
SMART Self Test [Enabled]
M.2_3 [Enabled]
M.2_3 Hot Plug [Disabled]
SATA6G_1 [Enabled]
SATA6G_1 Hot Plug [Disabled]
SATA6G_2 [Enabled]
SATA6G_2 Hot Plug [Disabled]
SATA6G_3 [Enabled]
SATA6G_3 Hot Plug [Disabled]
SATA6G_4 [Enabled]
SATA6G_4 Hot Plug [Disabled]
PTT [Enable]
Intel(R) Dynamic Tuning Technology [Disabled]
PCIE Tunneling over USB4 [Enabled]
Discrete Thunderbolt(TM) Support [Disabled]
Security Device Support [Enable]
SHA256 PCR Bank [Enabled]
Pending operation [None]
Platform Hierarchy [Enabled]
Storage Hierarchy [Enabled]
Endorsement Hierarchy [Enabled]
Physical Presence Spec Version [1.3]
USB Host Controller Support [Disabled]
Password protection of Runtime Variables [Enable]
Above 4G Decoding [Enabled]
Resize BAR Support [Enabled]
SR-IOV Support [Disabled]
Legacy USB Support [Enabled]
XHCI Hand-off [Enabled]
JetFlashTranscend 8GB 1.00 [Auto]
U10G_1 [Enabled]
U5G_E5 [Enabled]
U5G_E6 [Enabled]
U5G_E7 [Enabled]
U5G_E8 [Enabled]
U20G_C3 [Enabled]
U10G_5 [Enabled]
U10G_6 [Enabled]
U10G_7 [Enabled]
U10G_8 [Enabled]
U20G_C9 [Enabled]
USB11 [Enabled]
USB12 [Enabled]
U32G1_E1 [Enabled]
U32G1_E2 [Enabled]
U32G1_E3 [Enabled]
U32G1_E4 [Enabled]
Network Stack [Disabled]
Device [WDC WD30EFRX-68AX9N0]
Restore AC Power Loss [Power Off]
Max Power Saving [Disabled]
ErP Ready [Disabled]
Power On By PCI-E [Disabled]
Power On By RTC [Disabled]
PCIe Bandwidth Bifurcation Configuration [Auto]
USB Audio [Enabled]
Intel LAN [Enabled]
USB power delivery in Soft Off state (S5) [Disabled]
Wi-Fi Controller [Disabled]
Bluetooth Controller [Disabled]
When system is in working state [All On]
Q-Code LED Function [Auto]
When system is in sleep, hibernate or soft off states [Stealth Mode]
M.2_3 Configuration [Auto]
CPU PCIE Configuration Mode [Auto]
ASMedia USB 3.2 Controller_U5G_E12 [Enabled]
ASMedia USB 3.2 Controller_U5G_E34 [Enabled]
GNA Device [Disabled]
Alteration Mode Switch [PCIE Link Speed]
CPU Temperature [Monitor]
CPU Package Temperature [Monitor]
MotherBoard Temperature [Monitor]
VRM Temperature [Monitor]
Chipset Temperature [Monitor]
T_Sensor Temperature [Monitor]
DIMM.2 Sensor 1 Temperature [Monitor]
DIMM.2 Sensor 2 Temperature [Monitor]
Water In T Sensor Temperature [Monitor]
Water Out T Sensor Temperature [Monitor]
DIMM Thermistor Temperature [Monitor]
DIMM A1 Temperature [Monitor]
DIMM B1 Temperature [Monitor]
CPU Fan Speed [Monitor]
CPU Optional Fan Speed [Monitor]
Chassis Fan 1 Speed [Monitor]
Chassis Fan 2 Speed [Monitor]
Extra Flow Fan Speed [Monitor]
Water Pump+ Speed [Monitor]
AIO Pump Speed [Monitor]
Flow Rate [Monitor]
CPU Core Voltage [Monitor]
12V Voltage [Monitor]
5V Voltage [Monitor]
3.3V Voltage [Monitor]
Memory Controller Voltage [Monitor]
CPU Fan Q-Fan Control [PWM Mode]
CPU Fan Profile [Manual]
CPU Fan Q-Fan Source [CPU]
CPU Fan Step Up [Level 0]
CPU Fan Step Down [Level 0]
CPU Fan Speed Low Limit [200 RPM]
CPU Fan Point4 Temperature [70]
CPU Fan Point4 Duty Cycle (%) [50]
CPU Fan Point3 Temperature [65]
CPU Fan Point3 Duty Cycle (%) [50]
CPU Fan Point2 Temperature [45]
CPU Fan Point2 Duty Cycle (%) [50]
CPU Fan Point1 Temperature [20]
CPU Fan Point1 Duty Cycle (%) [50]
Chassis Fan 1 Q-Fan Control [Auto Detect]
Chassis Fan 1 Profile [Standard]
Chassis Fan 1 Q-Fan Source [CPU]
Chassis Fan 1 Step Up [Level 0]
Chassis Fan 1 Step Down [Level 0]
Chassis Fan 1 Speed Low Limit [200 RPM]
Chassis Fan 2 Q-Fan Control [PWM Mode]
Chassis Fan 2 Profile [Manual]
Chassis Fan 2 Q-Fan Source [CPU]
Chassis Fan 2 Step Up [Level 0]
Chassis Fan 2 Step Down [Level 0]
Chassis Fan 2 Speed Low Limit [200 RPM]
Chassis Fan 2 Point4 Temperature [70]
Chassis Fan 2 Point4 Duty Cycle (%) [42]
Chassis Fan 2 Point3 Temperature [65]
Chassis Fan 2 Point3 Duty Cycle (%) [42]
Chassis Fan 2 Point2 Temperature [45]
Chassis Fan 2 Point2 Duty Cycle (%) [42]
Chassis Fan 2 Point1 Temperature [20]
Chassis Fan 2 Point1 Duty Cycle (%) [42]
Extra Flow Fan Q-Fan Control [Auto Detect]
Extra Flow Fan Profile [Standard]
Extra Flow Fan Q-Fan Source [DIMM Thermistor]
Extra Flow Fan Step Up [Level 0]
Extra Flow Fan Step Down [Level 0]
Extra Flow Fan Speed Low Limit [Ignore]
Water Pump+ Q-Fan Control [Auto Detect]
Water Pump+ Profile [Full Speed]
AIO Pump Q-Fan Control [Auto Detect]
AIO Pump Profile [Full Speed]
CPU Temperature LED Switch [Enabled]
Launch CSM [Disabled]
OS Type [Windows UEFI mode]
Secure Boot Mode [Standard]
Fast Boot [Disabled]
Boot Logo Display [Auto]
POST Delay Time [3 sec]
Bootup NumLock State [On]
Wait For 'F1' If Error [Enabled]
Option ROM Messages [Force BIOS]
Interrupt 19 Capture [Disabled]
AMI Native NVMe Driver Support [Enabled]
Setup Mode [Advanced Mode]
Boot Sector (MBR/GPT) Recovery Policy [Local User Control]
Next Boot Recovery Action [Skip]
BIOS Image Rollback Support [Enabled]
Publish HII Resources [Disabled]
Flexkey [Reset]
Setup Animator [Disabled]
Load from Profile [2]
Profile Name [7800]
Save to Profile [3]
DIMM Slot Number [DIMM_A1]
Hotkey F3 [Toggle ASUS EZ Flash 3]
Hotkey F4 [Boot from UEFI USB]
Download & Install ARMOURY CRATE app [Disabled]
Download & Install MyASUS service & app [Disabled]

tibcsi0407 schrieb:
Never saw it dropping that huge. Even on very unstable environment it stays around the set value.
Look at his two per channel test above, both stays around 1.32V.
Zum Vergrößern anklicken....
I think it only drops while at idle. Dont know if it should do that or not though.
 
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Darkthrone schrieb:
It can pass everything and CB15 Extreme no issues. I feed it with 1.1208-1.137v under load just for VST/VT3 while it only needs like 1.09-1.1v for 56/44/44

[2024/05/28 14:13:51]
Ai Overclock Tuner [XMP II]
XMP [DDR5-7200 34-42-42-84-2N-1.40V-1.40V]
BCLK Frequency [100.0000]
PCIE Frequency [100.0000]
Intel(R) Adaptive Boost Technology [Auto]
ASUS MultiCore Enhancement [Auto – Lets BIOS Optimize]
SVID Behavior [Auto]
BCLK Frequency : DRAM Frequency Ratio [Auto]
Memory Controller : DRAM Frequency Ratio [Auto]
DRAM Frequency [DDR5-8000MHz]
DIMM Flex [Disabled]
Performance Core Ratio [Sync All Cores]
ALL-Core Ratio Limit [56]
Performance Core0 Specific Ratio Limit [Auto]
Performance Core0 specific Voltage [Auto]
Performance Core1 Specific Ratio Limit [Auto]
Performance Core1 specific Voltage [Auto]
Performance Core2 Specific Ratio Limit [Auto]
Performance Core2 specific Voltage [Auto]
Performance Core3 Specific Ratio Limit [Auto]
Performance Core3 specific Voltage [Auto]
*Performance Core4 Specific Ratio Limit [Auto]
Performance Core4 specific Voltage [Auto]
*Performance Core5 Specific Ratio Limit [Auto]
Performance Core5 specific Voltage [Auto]
Performance Core6 Specific Ratio Limit [Auto]
Performance Core6 specific Voltage [Auto]
Performance Core7 Specific Ratio Limit [Auto]
Performance Core7 specific Voltage [Auto]
Efficient Core Ratio [Sync All Cores]
ALL-Core Ratio Limit [44]
Efficient Core Group0 Specific Ratio Limit [Auto]
Efficient Core Group0 specific Voltage [Auto]
Efficient Core Group1 Specific Ratio Limit [Auto]
Efficient Core Group1 specific Voltage [Auto]
Efficient Core Group2 Specific Ratio Limit [Auto]
Efficient Core Group2 specific Voltage [Auto]
Efficient Core Group3 Specific Ratio Limit [Auto]
Efficient Core Group3 specific Voltage [Auto]
AVX2 [Auto]
AVX2 Ratio Offset to per-core Ratio Limit [Auto]
AVX2 Voltage Guardband Scale Factor [Auto]
Maximus Tweak [Mode 2]
DRAM CAS# Latency [36]
DRAM RAS# to CAS# Delay Read [48]
DRAM RAS# to CAS# Delay Write [48]
DRAM RAS# PRE Time [48]
DRAM RAS# ACT Time [60]
DRAM Command Rate [2N]
DRAM RAS# to RAS# Delay L [10]
DRAM RAS# to RAS# Delay S [8]
DRAM REF Cycle Time 2 [512]
DRAM REF Cycle Time Same Bank [416]
DRAM Refresh Interval [65535]
DRAM WRITE Recovery Time [Auto]
DRAM READ to PRE Time [12]
DRAM FOUR ACT WIN Time [32]
DRAM WRITE to READ Delay L [Auto]
DRAM WRITE to READ Delay S [Auto]
DRAM CKE Minimum Pulse Width [20]
DRAM Write Latency [34]
Ctl0 dqvrefup [Auto]
Ctl0 dqvrefdn [Auto]
Ctl0 dqodtvrefup [Auto]
Ctl0 dqodtvrefdn [Auto]
Ctl1 cmdvrefup [Auto]
Ctl1 ctlvrefup [Auto]
Ctl1 clkvrefup [Auto]
Ctl1 ckecsvrefup [Auto]
Ctl2 cmdvrefdn [Auto]
Ctl2 ctlvrefdn [Auto]
Ctl2 clkvrefdn [Auto]
Read Equalization RxEq Start Sign [-]
Read Equalization RxEq Start [Auto]
Read Equalization RxEq Stop Sign [-]
Read Equalization RxEq Stop [Auto]
ODT_READ_DURATION [Auto]
ODT_READ_DELAY [Auto]
ODT_WRITE_DURATION [Auto]
ODT_WRITE_DELAY [Auto]
DQ RTT WR [Auto]
DQ RTT NOM RD [Auto]
DQ RTT NOM WR [Auto]
DQ RTT PARK [Auto]
DQ RTT PARK DQS [Auto]
GroupA CA ODT [Auto]
GroupA CS ODT [Auto]
GroupA CK ODT [Auto]
GroupB CA ODT [Auto]
GroupB CS ODT [Auto]
GroupB CK ODT [Auto]
Pull-up Output Driver Impedance [Auto]
Pull-Down Output Driver Impedance [Auto]
DQ RTT WR [Auto]
DQ RTT NOM RD [Auto]
DQ RTT NOM WR [Auto]
DQ RTT PARK [Auto]
DQ RTT PARK DQS [Auto]
GroupA CA ODT [Auto]
GroupA CS ODT [Auto]
GroupA CK ODT [Auto]
GroupB CA ODT [Auto]
GroupB CS ODT [Auto]
GroupB CK ODT [Auto]
Pull-up Output Driver Impedance [Auto]
Pull-Down Output Driver Impedance [Auto]
Round Trip Latency Init Value MC0 CHA [Auto]
Round Trip Latency Max Value MC0 CHA [Auto]
Round Trip Latency Offset Value Mode Sign MC0 CHA [-]
Round Trip Latency Offset Value MC0 CHA [Auto]
Round Trip Latency Init Value MC0 CHB [Auto]
Round Trip Latency Max Value MC0 CHB [Auto]
Round Trip Latency Offset Value Mode Sign MC0 CHB [-]
Round Trip Latency Offset Value MC0 CHB [Auto]
Round Trip Latency Init Value MC1 CHA [Auto]
Round Trip Latency Max Value MC1 CHA [Auto]
Round Trip Latency Offset Value Mode Sign MC1 CHA [-]
Round Trip Latency Offset Value MC1 CHA [Auto]
Round Trip Latency Init Value MC1 CHB [Auto]
Round Trip Latency Max Value MC1 CHB [Auto]
Round Trip Latency Offset Value Mode Sign MC1 CHB [-]
Round Trip Latency Offset Value MC1 CHB [Auto]
Round Trip Latency MC0 CHA R0 [Auto]
Round Trip Latency MC0 CHA R1 [Auto]
Round Trip Latency MC0 CHA R2 [0]
Round Trip Latency MC0 CHA R3 [0]
Round Trip Latency MC0 CHA R4 [0]
Round Trip Latency MC0 CHA R5 [0]
Round Trip Latency MC0 CHA R6 [0]
Round Trip Latency MC0 CHA R7 [0]
Round Trip Latency MC0 CHB R0 [Auto]
Round Trip Latency MC0 CHB R1 [Auto]
Round Trip Latency MC0 CHB R2 [0]
Round Trip Latency MC0 CHB R3 [0]
Round Trip Latency MC0 CHB R4 [0]
Round Trip Latency MC0 CHB R5 [0]
Round Trip Latency MC0 CHB R6 [0]
Round Trip Latency MC0 CHB R7 [0]
Round Trip Latency MC1 CHA R0 [Auto]
Round Trip Latency MC1 CHA R1 [Auto]
Round Trip Latency MC1 CHA R2 [0]
Round Trip Latency MC1 CHA R3 [0]
Round Trip Latency MC1 CHA R4 [0]
Round Trip Latency MC1 CHA R5 [0]
Round Trip Latency MC1 CHA R6 [0]
Round Trip Latency MC1 CHA R7 [0]
Round Trip Latency MC1 CHB R0 [Auto]
Round Trip Latency MC1 CHB R1 [Auto]
Round Trip Latency MC1 CHB R2 [0]
Round Trip Latency MC1 CHB R3 [0]
Round Trip Latency MC1 CHB R4 [0]
Round Trip Latency MC1 CHB R5 [0]
Round Trip Latency MC1 CHB R6 [0]
Round Trip Latency MC1 CHB R7 [0]
Early Command Training [Auto]
SenseAmp Offset Training [Auto]
Early ReadMPR Timing Centering 2D [Auto]
Read MPR Training [Auto]
Receive Enable Training [Auto]
Jedec Write Leveling [Auto]
Early Write Time Centering 2D [Auto]
Early Read Time Centering 2D [Auto]
Write Timing Centering 1D [Auto]
Write Voltage Centering 1D [Auto]
Read Timing Centering 1D [Auto]
Read Timing Centering with JR [Auto]
Dimm ODT Training* [Auto]
Max RTT_WR [ODT Off]
DIMM RON Training* [Auto]
Write Drive Strength/Equalization 2D* [Auto]
Write Slew Rate Training* [Auto]
Read ODT Training* [Auto]
Comp Optimization Training [Auto]
Read Equalization Training* [Auto]
Read Amplifier Training* [Auto]
Write Timing Centering 2D [Auto]
Read Timing Centering 2D [Auto]
Command Voltage Centering [Auto]
Early Command Voltage Centering [Auto]
Write Voltage Centering 2D [Auto]
Read Voltage Centering 2D [Auto]
Late Command Training [Auto]
Round Trip Latency [Auto]
Turn Around Timing Training [Auto]
CMD CTL CLK Slew Rate [Auto]
CMD/CTL DS & E 2D [Auto]
Read Voltage Centering 1D [Auto]
TxDqTCO Comp Training* [Auto]
ClkTCO Comp Training* [Auto]
TxDqsTCO Comp Training* [Auto]
VccDLL Bypass Training [Auto]
CMD/CTL Drive Strength Up/Dn 2D [Auto]
DIMM CA ODT Training [Auto]
PanicVttDnLp Training* [Auto]
Read Vref Decap Training* [Auto]
Vddq Training [Disabled]
Duty Cycle Correction Training [Auto]
Periodic DCC [Auto]
Rank Margin Tool Per Bit [Auto]
DIMM DFE Training [Auto]
EARLY DIMM DFE Training [Auto]
Tx Dqs Dcc Training [Auto]
DRAM DCA Training [Auto]
Write Driver Strength Training [Auto]
Rank Margin Tool [Auto]
Memory Test [Auto]
DIMM SPD Alias Test [Auto]
Receive Enable Centering 1D [Auto]
Retrain Margin Check [Auto]
Write Drive Strength Up/Dn independently [Auto]
LPDDR DqDqs Re-Training [Auto]
Margin Check Limit [Disabled]
tRDRD_sg_Training [Auto]
tRDRD_sg_Runtime [16]
tRDRD_dg_Training [Auto]
tRDRD_dg_Runtime [8]
tRDWR_sg [20]
tRDWR_dg [20]
tWRWR_sg [16]
tWRWR_dg [8]
tWRRD_sg [64]
tWRRD_dg [54]
tRDRD_dr [0]
tRDRD_dd [0]
tRDWR_dr [0]
tRDWR_dd [0]
tWRWR_dr [0]
tWRWR_dd [0]
tWRRD_dr [0]
tWRRD_dd [0]
tRPRE [Auto]
tWPRE [Auto]
tWPOST [Auto]
tWRPRE [65]
tPRPDEN [2]
tRDPDEN [45]
tWRPDEN [66]
tCPDED [20]
tREFIX9 [Auto]
Ref Interval [Auto]
tXPDLL [Auto]
tXP [30]
tPPD [2]
tCCD_L_tDLLK [Auto]
tZQCAL [Auto]
tZQCS [Auto]
OREF_RI [Auto]
Refresh Watermarks [High]
Refresh Hp Wm [Auto]
Refresh Panic Wm [Auto]
Refresh Abr Release [Auto]
tXSDLL [Auto]
tZQOPER [Auto]
tMOD [Auto]
CounttREFIWhileRefEn [Auto]
HPRefOnMRS [Auto]
SRX Ref Debits [Auto]
RAISE BLK WAIT [Auto]
Ref Stagger En [Auto]
Ref Stagger Mode [Auto]
Disable Stolen Refresh [Auto]
En Ref Type Display [Auto]
Trefipulse Stagger Disable [Auto]
tRPab ext [Auto]
derating ext [Auto]
Allow 2cyc B2B LPDDR [Auto]
tCSH [Auto]
tCSL [Auto]
powerdown Enable [Auto]
idle length [Auto]
raise cke after exit latency [Auto]
powerdown latency [Auto]
powerdown length [Auto]
selfrefresh latency [Auto]
selfrefresh length [Auto]
ckevalid length [Auto]
ckevalid enable [Auto]
idle enable [Auto]
selfrefresh enable [Auto]
Address mirror [Auto]
no gear4 param divide [Auto]
x8 device [Auto]
no gear2 param divide [Auto]
ddr 1dpc split ranks on subch [Auto]
write0 enable [Auto]
MultiCycCmd [Auto]
WCKDiffLowInIdle [Auto]
PBR Disable [Auto]
PBR OOO Dis [Auto]
PBR Disable on hot [Auto]
PBR Exit on Idle Cnt [Auto]
tXSR [519]
Dec tCWL [Auto]
Add tCWL [Auto]
Add 1Qclk delay [Auto]
MRC Fast Boot [Disabled]
MCH Full Check [Auto]
Mem Over Clock Fail Count [1]
Training Profile [Standard Profile]
RxDfe [Auto]
Mrc Training Loop Count [Auto]
DRAM CLK Period [Auto]
Dll_bwsel [Auto]
Controller 0, Channel 0 Control [Enabled]
Controller 0, Channel 1 Control [Enabled]
Controller 1, Channel 0 Control [Enabled]
Controller 1, Channel 1 Control [Enabled]
MC_Vref0 [Auto]
MC_Vref1 [Auto]
MC_Vref2 [Auto]
Fine Granularity Refresh mode [Auto]
SDRAM Density Per Die [Auto]
SDRAM Banks Per Bank Group [Auto]
SDRAM Bank Groups [Auto]
Dynamic Memory Boost [Disabled]
Realtime Memory Frequency [Disabled]
SA GV [Disabled]
Voltage Monitor [Die Sense]
VRM Initialization Check [Enabled]
CPU Input Voltage Load-line Calibration [Level 3]
CPU Load-line Calibration [Level 5]
Synch ACDC Loadline with VRM Loadline [Disabled]
CPU Current Capability [140%]
CPU Current Reporting [100%]
Core Voltage Suspension [Auto]
CPU VRM Switching Frequency [Manual]
Fixed CPU VRM Switching Frequency(KHz) [500]
CPU Power Duty Control [Extreme]
CPU Power Phase Control [Extreme]
CPU Power Thermal Control [125]
CPU Core/Cache Boot Voltage [Auto]
CPU Input Boot Voltage [Auto]
PLL Termination Boot Voltage [Auto]
CPU Standby Boot Voltage [Auto]
Memory Controller Boot Voltage [Auto]
CPU Core Auto Voltage Cap [Auto]
CPU Input Auto Voltage Cap [Auto]
Memory Controller Auto Voltage Cap [Auto]
Maximum CPU Core Temperature [Auto]
Fast Throttle Threshold [Auto]
Package Temperature Threshold [Auto]
Regulate Frequency by above Threshold [Auto]
IVR Transmitter VDDQ ICCMAX [15]
Unlimited ICCMAX [Disabled]
CPU Core/Cache Current Limit Max. [400.00]
Long Duration Package Power Limit [253]
Package Power Time Window [Auto]
Short Duration Package Power Limit [320]
Dual Tau Boost [Disabled]
IA AC Load Line [Auto]
IA DC Load Line [Auto]
IA CEP [Disabled]
SA CEP [Disabled]
IA SoC Iccmax Reactive Protector [Auto]
Inverse Temperature Dependency Throttle [Auto]
IA VR Voltage Limit [1550]
CPU SVID Support [Auto]
Cache Dynamic OC Switcher [Auto]
TVB Voltage Optimizations [Auto]
Enhanced TVB [Auto]
Overclocking TVB [Auto]
Overclocking TVB Global Temperature Offset Sign [+]
Overclocking TVB Global Temperature Offset Value [Auto]
Offset Mode Sign 1 [+]
V/F Point 1 Offset [Auto]
Offset Mode Sign 2 [+]
V/F Point 2 Offset [Auto]
Offset Mode Sign 3 [+]
V/F Point 3 Offset [Auto]
Offset Mode Sign 4 [+]
V/F Point 4 Offset [Auto]
Offset Mode Sign 5 [+]
V/F Point 5 Offset [Auto]
Offset Mode Sign 6 [+]
V/F Point 6 Offset [Auto]
Offset Mode Sign 7 [+]
V/F Point 7 Offset [Auto]
Offset Mode Sign 8 [+]
V/F Point 8 Offset [Auto]
Offset Mode Sign 9 [+]
V/F Point 9 Offset [Auto]
Offset Mode Sign 10 [+]
V/F Point 10 Offset [Auto]
Offset Mode Sign 11 [+]
V/F Point 11 Offset [Auto]
Initial BCLK Frequency [100.0000]
Runtime BCLK OC [Disabled]
BCLK Amplitude [900mV]
BCLK Slew Rate [Fast]
BCLK Spread Spectrum [Disabled]
Initial PCIE Frequency [Auto]
PCIE/DMI Amplitude [900mV]
PCIE/DMI Slew Rate [Fast]
PCIE/DMI Spread Spectrum [Disabled]
Cold Boot PCIE Frequency [Auto]
Realtime Memory Timing [Enabled]
SPD Write Disable [TRUE]
PVD Ratio Threshold [Auto]
SA PLL Frequency Override [Auto]
BCLK TSC HW Fixup [Enabled]
Core Ratio Extension Mode [Disabled]
FLL OC mode [Auto]
UnderVolt Protection [Disabled]
Switch Microcode [Current Microcode]
Xtreme Tweaking [Disabled]
Core PLL Voltage [Auto]
GT PLL Voltage [Auto]
Ring PLL Voltage [Auto]
System Agent PLL Voltage [Auto]
Memory Controller PLL Voltage [Auto]
Efficient-core PLL Voltage [Auto]
CPU 1.8V Small Rail [Auto]
PLL Termination Voltage [Auto]
CPU Standby Voltage [Auto]
PCH 1.05V Voltage [Auto]
PCH 0.82V Voltage [Auto]
CPU Input Voltage Reset Voltage [Auto]
Eventual CPU Input Voltage [Auto]
Eventual Memory Controller Voltage [Auto]
Package Temperature Threshold [Auto]
Regulate Frequency by above Threshold [Auto]
Cooler Efficiency Customize [Keep Training]
Cooler Re-evaluation Algorithm [Normal]
Optimism Scale [100]
Ring Down Bin [Auto]
Min. CPU Cache Ratio [44]
Max. CPU Cache Ratio [44]
BCLK Aware Adaptive Voltage [Auto]
Actual VRM Core Voltage [Auto]
Global Core SVID Voltage [Adaptive Mode]
- Offset Mode Sign [-]
- Additional Turbo Mode CPU Core Voltage [Auto]
- Offset Voltage [0.04000]
Cache SVID Voltage [Auto]
CPU L2 Voltage [Auto]
CPU System Agent Voltage [Manual Mode]
- CPU System Agent Voltage Override [1.20000]
CPU Input Voltage [Auto]
High DRAM Voltage Mode [Enabled]
DRAM VDD Voltage [1.45000]
DRAM VDDQ Voltage [1.40000]
IVR Transmitter VDDQ Voltage [1.30000]
Memory Controller Voltage [1.40000]
MC Voltage Calculation Voltage Base [Auto]
VDD Calculation Voltage Base [Auto]
PMIC Voltages [Sync All PMICs]
SPD HUB VLDO (1.8V) [Auto]
SPD HUB VDDIO (1.0V) [Auto]
DRAM VDD Voltage [1.45000]
DRAM VDDQ Voltage [1.40000]
DRAM VPP Voltage [1.80000]
DRAM VDD Switching Frequency [Auto]
DRAM VDDQ Switching Frequency [Auto]
DRAM VPP Switching Frequency [Auto]
DRAM Current Capability [Auto]
PCI Express Native Power Management [Disabled]
DMI Link ASPM Control [Disabled]
ASPM [Disabled]
L1 Substates [Disabled]
DMI ASPM [Disabled]
DMI Gen3 ASPM [Disabled]
PEG - ASPM [Disabled]
PCI Express Clock Gating [Enabled]
Hardware Prefetcher [Enabled]
Adjacent Cache Line Prefetch [Disabled]
Intel (VMX) Virtualization Technology [Disabled]
Per P-Core Control [Disabled]
Per E-Core Control [Disabled]
Active Performance Cores [All]
Active Efficient Cores [All]
Hyper-Threading [Disabled]
Total Memory Encryption [Disabled]
Legacy Game Compatibility Mode [Disabled]
Boot performance mode [Auto]
Intel(R) SpeedStep(tm) [Disabled]
Intel(R) Speed Shift Technology [Disabled]
Turbo Mode [Enabled]
Acoustic Noise Mitigation [Disabled]
CPU C-states [Enabled]
Enhanced C-states [Enabled]
Package C State Limit [C8]
Thermal Monitor [Enabled]
Dual Tau Boost [Disabled]
VT-d [Disabled]
Memory Remap [Enabled]
Enable VMD controller [Enabled]
Map PCIe Storage under VMD [Disabled]
Map SATA Controller under VMD [Disabled]
M.2_2 Link Speed [Auto]
PCIEX16(G5)_1 Link Speed [Auto]
M.2_1 Link Speed [Auto]
PCIEX4(G4)_1 Link Speed [Auto]
PCIEX4(G4)_2 Link Speed [Auto]
M.2_3 Link Speed [Auto]
DIMM.2_1 Link Speed [Auto]
DIMM.2_2 Link Speed [Auto]
SATA Controller(s) [Enabled]
Aggressive LPM Support [Disabled]
SMART Self Test [Enabled]
M.2_3 [Enabled]
M.2_3 Hot Plug [Disabled]
SATA6G_1 [Enabled]
SATA6G_1 Hot Plug [Disabled]
SATA6G_2 [Enabled]
SATA6G_2 Hot Plug [Disabled]
SATA6G_3 [Enabled]
SATA6G_3 Hot Plug [Disabled]
SATA6G_4 [Enabled]
SATA6G_4 Hot Plug [Disabled]
PTT [Enable]
Intel(R) Dynamic Tuning Technology [Disabled]
PCIE Tunneling over USB4 [Enabled]
Discrete Thunderbolt(TM) Support [Disabled]
Security Device Support [Enable]
SHA256 PCR Bank [Enabled]
Pending operation [None]
Platform Hierarchy [Enabled]
Storage Hierarchy [Enabled]
Endorsement Hierarchy [Enabled]
Physical Presence Spec Version [1.3]
USB Host Controller Support [Disabled]
Password protection of Runtime Variables [Enable]
Above 4G Decoding [Enabled]
Resize BAR Support [Enabled]
SR-IOV Support [Disabled]
Legacy USB Support [Enabled]
XHCI Hand-off [Enabled]
JetFlashTranscend 8GB 1.00 [Auto]
U10G_1 [Enabled]
U5G_E5 [Enabled]
U5G_E6 [Enabled]
U5G_E7 [Enabled]
U5G_E8 [Enabled]
U20G_C3 [Enabled]
U10G_5 [Enabled]
U10G_6 [Enabled]
U10G_7 [Enabled]
U10G_8 [Enabled]
U20G_C9 [Enabled]
USB11 [Enabled]
USB12 [Enabled]
U32G1_E1 [Enabled]
U32G1_E2 [Enabled]
U32G1_E3 [Enabled]
U32G1_E4 [Enabled]
Network Stack [Disabled]
Device [WDC WD30EFRX-68AX9N0]
Restore AC Power Loss [Power Off]
Max Power Saving [Disabled]
ErP Ready [Disabled]
Power On By PCI-E [Disabled]
Power On By RTC [Disabled]
PCIe Bandwidth Bifurcation Configuration [Auto]
USB Audio [Enabled]
Intel LAN [Enabled]
USB power delivery in Soft Off state (S5) [Disabled]
Wi-Fi Controller [Disabled]
Bluetooth Controller [Disabled]
When system is in working state [All On]
Q-Code LED Function [Auto]
When system is in sleep, hibernate or soft off states [Stealth Mode]
M.2_3 Configuration [Auto]
CPU PCIE Configuration Mode [Auto]
ASMedia USB 3.2 Controller_U5G_E12 [Enabled]
ASMedia USB 3.2 Controller_U5G_E34 [Enabled]
GNA Device [Disabled]
Alteration Mode Switch [PCIE Link Speed]
CPU Temperature [Monitor]
CPU Package Temperature [Monitor]
MotherBoard Temperature [Monitor]
VRM Temperature [Monitor]
Chipset Temperature [Monitor]
T_Sensor Temperature [Monitor]
DIMM.2 Sensor 1 Temperature [Monitor]
DIMM.2 Sensor 2 Temperature [Monitor]
Water In T Sensor Temperature [Monitor]
Water Out T Sensor Temperature [Monitor]
DIMM Thermistor Temperature [Monitor]
DIMM A1 Temperature [Monitor]
DIMM B1 Temperature [Monitor]
CPU Fan Speed [Monitor]
CPU Optional Fan Speed [Monitor]
Chassis Fan 1 Speed [Monitor]
Chassis Fan 2 Speed [Monitor]
Extra Flow Fan Speed [Monitor]
Water Pump+ Speed [Monitor]
AIO Pump Speed [Monitor]
Flow Rate [Monitor]
CPU Core Voltage [Monitor]
12V Voltage [Monitor]
5V Voltage [Monitor]
3.3V Voltage [Monitor]
Memory Controller Voltage [Monitor]
CPU Fan Q-Fan Control [PWM Mode]
CPU Fan Profile [Manual]
CPU Fan Q-Fan Source [CPU]
CPU Fan Step Up [Level 0]
CPU Fan Step Down [Level 0]
CPU Fan Speed Low Limit [200 RPM]
CPU Fan Point4 Temperature [70]
CPU Fan Point4 Duty Cycle (%) [50]
CPU Fan Point3 Temperature [65]
CPU Fan Point3 Duty Cycle (%) [50]
CPU Fan Point2 Temperature [45]
CPU Fan Point2 Duty Cycle (%) [50]
CPU Fan Point1 Temperature [20]
CPU Fan Point1 Duty Cycle (%) [50]
Chassis Fan 1 Q-Fan Control [Auto Detect]
Chassis Fan 1 Profile [Standard]
Chassis Fan 1 Q-Fan Source [CPU]
Chassis Fan 1 Step Up [Level 0]
Chassis Fan 1 Step Down [Level 0]
Chassis Fan 1 Speed Low Limit [200 RPM]
Chassis Fan 2 Q-Fan Control [PWM Mode]
Chassis Fan 2 Profile [Manual]
Chassis Fan 2 Q-Fan Source [CPU]
Chassis Fan 2 Step Up [Level 0]
Chassis Fan 2 Step Down [Level 0]
Chassis Fan 2 Speed Low Limit [200 RPM]
Chassis Fan 2 Point4 Temperature [70]
Chassis Fan 2 Point4 Duty Cycle (%) [42]
Chassis Fan 2 Point3 Temperature [65]
Chassis Fan 2 Point3 Duty Cycle (%) [42]
Chassis Fan 2 Point2 Temperature [45]
Chassis Fan 2 Point2 Duty Cycle (%) [42]
Chassis Fan 2 Point1 Temperature [20]
Chassis Fan 2 Point1 Duty Cycle (%) [42]
Extra Flow Fan Q-Fan Control [Auto Detect]
Extra Flow Fan Profile [Standard]
Extra Flow Fan Q-Fan Source [DIMM Thermistor]
Extra Flow Fan Step Up [Level 0]
Extra Flow Fan Step Down [Level 0]
Extra Flow Fan Speed Low Limit [Ignore]
Water Pump+ Q-Fan Control [Auto Detect]
Water Pump+ Profile [Full Speed]
AIO Pump Q-Fan Control [Auto Detect]
AIO Pump Profile [Full Speed]
CPU Temperature LED Switch [Enabled]
Launch CSM [Disabled]
OS Type [Windows UEFI mode]
Secure Boot Mode [Standard]
Fast Boot [Disabled]
Boot Logo Display [Auto]
POST Delay Time [3 sec]
Bootup NumLock State [On]
Wait For 'F1' If Error [Enabled]
Option ROM Messages [Force BIOS]
Interrupt 19 Capture [Disabled]
AMI Native NVMe Driver Support [Enabled]
Setup Mode [Advanced Mode]
Boot Sector (MBR/GPT) Recovery Policy [Local User Control]
Next Boot Recovery Action [Skip]
BIOS Image Rollback Support [Enabled]
Publish HII Resources [Disabled]
Flexkey [Reset]
Setup Animator [Disabled]
Load from Profile [2]
Profile Name [7800]
Save to Profile [3]
DIMM Slot Number [DIMM_A1]
Hotkey F3 [Toggle ASUS EZ Flash 3]
Hotkey F4 [Boot from UEFI USB]
Download & Install ARMOURY CRATE app [Disabled]
Download & Install MyASUS service & app [Disabled]


I think it only drops while at idle. Dont know if it should do that or not though.
Zum Vergrößern anklicken....
Shouldn't drop in idle I believe. For me it doesn't even drop in a 12h workday on the pc.
 
tibcsi0407 schrieb:
Shouldn't drop in idle I believe. For me it doesn't even drop in a 12h workday on the PC.
Zum Vergrößern anklicken....
Restarted to save the bios for Veii and doesnt seem to have the drop now, weird...
TX.png
 
Darkthrone schrieb:
It can pass everything and CB15 Extreme no issues. I feed it with 1.1208-1.137v under load just for VST/VT3 while it only needs like 1.09-1.1v for 56/44/44
Zum Vergrößern anklicken....
The "needs more, feed it more" part
Was that purely by the SVID offset done ?
Or you did also factor it in the loadline

The loadline needs no touch , generally
And this thing is bad
1716896472183.png


Offset mode doesnt have to start at 0
Cache and so QCLK itself needs to downclock
By it downclocking yet you having high supply voltage for it, will be bad
You did not have high supply voltage in your case, but you dont allow it to clock gate
Basically this will cause instability, due to P-Core Curve limit already forcing a lower voltage state
And because that lower voltage state expects its own Ring Curve state + the stronger throttle due to you giving it even more voltage

All on all, it can be that you have less supply by adding supply vs zero added voltage and letting it remain dynamic.
As that offset messes with curve and that supply increases throttle factor :)

Soo work:
~ CPU LLC gone,
~ CPU switch freq , well its not needed APEX is tuned well out of the box
~ You only got 100mV delta between VDDQ's. Its too little.
MVDD 1455-1460mV
MVDDQ 1340mV
IVR VDDQ_IMC 1160mV
IVR VDD(2)_CPU 1350
 
Veii schrieb:
The "needs more, feed it more" part
Was that purely by the SVID offset done?
Or you also factored it into the loadline

The loadline needs no touch, generally
And this thing is bad
Anhang anzeigen 1001905

Offset mode doesn't have to start at 0
Cache and so QCLK itself needs to downclock
By downclocking it yet you having high supply voltage for it, will be bad
You did not have high supply voltage in your case, but you don't allow it to clock gate
Basically this will cause instability, due to P-Core Curve limit already forcing a lower voltage state
And because that lower voltage state expects its own Ring Curve state + the stronger throttle due to you giving it even more voltage

All on all, it can be that you have less supply by adding supply vs zero added voltage and letting it remain dynamic.
As this offset messes up with curve and supply increases throttle factor:)

Soo work:
~ CPU LLC gone,
~ CPU switch freq , well its not needed APEX is tuned well out of the box
~ You only got 100mV delta between VDDQ's. It's too little.
MVDD 1455-1460mV
MVDDQ 1340mV
IVR VDDQ_IMC 1160mV
IVR VDD(2)_CPU 1350
Zum Vergrößern anklicken....
Now I use LLC5, change it?
Min/Max CPU Cache 44/44, change?
Global Core Svid to Auto?

IVR VDDQ_IMC 1160mV, TX?
IVR VDD(2)_CPU 1350, MC?
 
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Darkthrone schrieb:
Everything as you said and SA 1.12v as tibcsi suggested boot fine. But failed instantly.
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Any score anything ?
please 1.15 SA

Then same voltage down to 7800.
Need to fix voltage/delta first before ever attempting 8000+
 
Veii schrieb:
Any score anything ?
please 1.15 SA

Then same voltage down to 7800.
Need to fix voltage/delta first before ever attempting 8000+
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LLC - Auto
Min/Max CPU Cache - Auto
Global Core Svid - Auto
CPU switch freq - Auto

SA at 1.15 fail after 5 sec, keep increasing by 0.01v?

7800 seems to work no matter what. Either at auto, low volt or high volt. I will try the same voltages at 7800 also.
 
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Veii schrieb:
Veii schrieb:
Here you have three things
Basic signal, signal drive+filter, signal phase+speed
You combine all 3 , to cover just one category change on signal alignment.
They are different things, slopes are not the resolve to everything. How its feed matters , not the opposite.
Not 100% confident on "E" meaning.

Then we have
www.overclock.net

*Official* Intel DDR5 OC and 24/7 daily Memory Stability...

www.overclock.net www.overclock.net
Using logic alone.

Your defined margins due to CTL0, aka your [Redacted] suggestions given by helper
Cause you no favor.
A point of a good VREF is a high margin.
You achieved the opposite by the person focusing soo much on pin-point stability, without factoring variance.
Your tuned values which they seems started to remake a 3rd time, probably just so they are different and can be "their own" again

Caused a limitation of margins, not an increase.
I advice to rethink that path & if corresponding researcher also reads that~~
Rethink the outcome by logic

If its indifferentiable to ASUS "high binned" tuning scenario (old),
How do we differentiate it again :-) like what was the achievement here.

We need more margins not less margins 🤭
And the least we need, is confidential data.
I don't know~

Anhang anzeigen 1001861Anhang anzeigen 1001862
See , blurring s*kks :)
Just a reminder that we go nowhere with this proprietary mentality.
And especially if researcher spends soo much lifetime for himself, just to keep things secret.

CTL1+CTL2 are different from CTL0.
If you+helper mess with CTL1+2, they mess with training delay and RTT.
If X messes with VPP, they mess with the same ~ training delay, voltage strength, and phase alignment
Falling into the same rabbit hole you are right now ~ inconsistent thermal variance and bad thermal stability.

Remember i push you to 100° y-cruncher stable ~ early days :)

Advice,
Probably dont bother.
You put your focus on the wrong path.
Especially as CTL0 ODT is sample unique, and here even by logic ~ will never be SA scaling.
Nor will be board to board or cpu to cpu replicable.
I don't know~
Beitrag automatisch zusammengeführt:

EDIT:
Given i remember this person and their way of work
I think they've fallen into the trap of learning from ASUS (rutool, hex) work and matching Down's as a flat thing.
This only functions if Board is build perfect, and even then, you can't just put a DOWN baseline and expect it to work

There are far too many outer factors, that prevent such a book-like perfect scenario (of tuning)
Book-like "perfect" tuning scenario only works @ the lab and design stage.
Yet even that will not guarantee perfect outcome without variance.

Soo even if lets say "i" was PCB designer and all checks pass.
They will never be identical in outcome past design and past silk step.

Now adding CPU variance and dynamic ODT to this topic.
You simply can not run them at the same duration and same endpoint.
That is for all that make DQ and all that make DQS.
Training exists because its required.

I think researcher fell into this rabbit hole.
Remembering old talk and seeing concurrent outcome (bad margins) :-)
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I saw no other path forward.

Voltage tuning alone gave retrain inconsistency along with temperature sensitivity. Profiles would pass 60 min on y-cruncher and then instantly error in y-cruncher on subsequent retrains.

Custom RTTs and RONs gave more consistency with retrains, but still variable where one training would do 30 minutes until error, next 18 min, next 45 min, etc. Temp sensitivity was still present.

After adding CTL0's and disabling those three training algorithms, some minor tweaks to SA and VDD2 were required but it gave consistent retrains, and temperature sensitivity remained.

It isn't the temps under load that are the issue, it is the temps present during training that it hinges upon. Core max rarely reaches 65C with this profile.
 
@Darkthrone

Full HWinfo, ASRock Timing Configurator & ASUS MemTweakit, and letting TM5 run until 3+ errors occur in screenshots would give more info so one can advise what to do.
 
Veii schrieb:
I need visual data :)
Not words~~
Cant else help properly.
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Ofc you do, i do my best with my limited free time :)
Here you go...

With SA at 1.12 speeds were all over the place and failed at loop 5...

VDD/Q 1.44/1.32
SA 1.13
TX 1.14
MC 1.35
7800veii.png


Now i will try with SA 1.14

CarSalesman schrieb:
@Darkthrone

Full HWinfo, ASRock Timing Configurator & ASUS MemTweakit, and letting TM5 run until 3+ errors occur in screenshots would give more info so one can advise what to do.
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One test at a time plz :) I will also run TM5
 
CarSalesman schrieb:
The bitrate looks decently strong and very consistent, so you are likely super close!
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Sun, 55/42/42 HT Off
VDD/Q1.44/1.32
SAT1.14
TX1.14
MC1.35

It passed a quick 10 loop stable, but while VST run faster, VT3 dropped from 1.22 to 1.06...

7800vst.png


EDIT: I opened chrome and rerun VT3 and went back to 1.22...
 
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Previous run was also with HT Off

Edit: As i said opened chrome and back to 1.22 with HT Off as you can see

122.png
 
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Darkthrone schrieb:
Previous run was also with HT Off

Edit: As i said opened chrome and back to 1.22 with HT Off as you can see

Anhang anzeigen 1002027
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I've been using task manager details tab to set Y-cruncher to high priority, HWinfo to above normal priority, and then right before you start test in y-cruncher it generates an additional process in details tab of task manager (it starts with the number 4, so easy to find if you sort processes by name), and I set that process to above normal as well.

This alleviates issue of the bitrate not being maxed out. If you don't put HWInfo on Above normal (to match the calculations' process) it freaks out and won't keep polling. And if you don't set y-cruncher to high priority, it won't properly report what is happening.
 
Darkthrone schrieb:
7800veii.png


Now i will try with SA 1.14
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Mmm its not too bad, but kind of not even close. (far too early for 8000)
Also thank you~
Your IVR VDDQ_IMC does vanish tho. Its strange.

Lets try something else
Before that, can you re'run MC SP 5x and check how todays state is.

I also notice you defined 18min as "done"
You need it at very very least to pass 45-90min. Else it has no weight.
45 being the bare minimum, but 90 is a better target.
One runs 4-5 loops only to verify TM5 will not spill out g*rbage and CPU instability influence it.
But ya for a full cpu stability-test its not enough.

When you're done and i can see at least near the 90min mark on y-cruncher
we'll try something else and more absurd.
Maybe your CPU likes it, currently tho i can not say its anywhere near close to stable.
And i want "today's" MC SP values ~ 5 runs one after another.

Also i don't think our extremely low voltages are to blame, but something else is unstable.

EDIT:
SA you can move in 5mV steps, but its not that. It would be waste of time.
CPU side very likely, yet not that.
Which dimms do you use ? Still the delta 7200s?

And also HT on~!
Don't downgrade your CPU to increase stability.
 
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Veii schrieb:
Mmm its not too bad, but kind of not even close. (far too early for 8000)
Also thank you~
Your IVR VDDQ_IMC does vanish tho. Its strange.

Lets try something else
Before that, can you re'run MC SP 5x and check how todays state is.

I also notice you defined 18min as "done"
You need it at very very least to pass 45-90min. Else it has no weight.
45 being the bare minimum, but 90 is a better target.
One runs 4-5 loops only to verify TM5 will not spill out g*rbage and CPU instability influence it.
But ya for a full cpu stability-test its not enough.

When you're done and i can see at least near the 90min mark on y-cruncher
we'll try something else and more absurd.
Maybe your CPU likes it, currently tho i can not say its anywhere near close to stable.
And i want "today's" MC SP values ~ 5 runs one after another.

Also i don't think our extremely low voltages are to blame, but something else is unstable.

EDIT:
SA you can move in 5mV steps, but its not that. It would be waste of time.
CPU side very likely, yet not that.
Which dimms do you use ? Still the delta 7200s?

And also HT on~!
Don't downgrade your CPU to increase stability.
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Since last time we checked i reinstalled the original ILM, i couldnt make TR contact frame to work correctly. Everyone say if you screw it down fully it works perfect but that was not the case with me. Anyway MC SP with ILM, 80-85-85-86-85-79-86

I only do 20min loops cause i only game/emails/forums/youtube on the pc. So this kind of stability is far more than i need :)
But i can try a 45 min run just for you...

Yes i still use the Teamgroup Delta 2x16GB 7200c34
Was thinking to get the 2x24GB 8200 Xtreem but dont know if its worth it if i cant even run 8000

I dont run HT on cause games dont really benefit from it. So lower volt/lower temps.

EDIT: Here is the 50 min run i promised...

I only changed SA from 1.14 i had yesterday, cause it failed on the first loop today (damn DDR5), to 1.135
VST50m.png
 
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@CarSalesman gave me an idea about 8400C34, so I tried it.
KF back in the slot (buying a new binned KS is in progress. :) ) So easy to work with this CPU compared to the bitchy KS.
MEM_VDD: 1.68V
MEM_VDDQ: 1.41V
CPU_VDDQ: 1.24V
SA: 1.12v
VDD2: 1.462V
RON: 48-40 / 40-48
Képernyőkép 2024-05-29 094101.png
 
Darkthrone schrieb:
80-85-85-86-85-79-86
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Yea it jumps too much still. Far too much

Sadly i don't know why IVR drops soo much but only VDDQ_IMC and not VDD2_CPU.
I am aware of how it behaves and it is a feature, with such big gap signaling an instability.
But it doesn't resolve so far. So we need more work.
Darkthrone schrieb:
I only do 20min loops cause i only game/emails/forums/youtube on the pc. So this kind of stability is far more than i need :)
But i can try a 45 min run just for you...
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I understand, but the problem is, laws of physics is unforgiving.
And you have too many variables already.
If we don't hold to protocol, what are we testing or doing here :-)

Doing it the lazy way will complicate things and people will not take you serious
Not because it might not need to be stable, but because your data becomes invalid.
Hence the actions and recommendations become invalid.

Thermal discharge to room is a thing, and thermal caused reflections are a thing.
All have a nice round number of 90min, when they can or can not appear
Unless your open bench sits in a huge warehouse or so.
Nevertheless you have VRM inefficiency, substrate leakage and internal jumps
And the very basic "thermal equilibrium" law. Where usually AIOs take 10-15min only to equalize.
Just equalization is not the whole picture.

Basically hold to 90min, and you are fine.
Test 4-6h, to make sure any type of ErrorCorrection doesn't bother. Not needed for you tho.
Only needed for researcher like me, who learn from the hardware. Else data collected is invalid.
We want our data and wasted electricity to have any validity right ? Soo follow protocols 🤭
Tbh it doesnt matter which hardware-part you test, but thats the timeframe you need to run it.
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@tibcsi0407 do you have trouble with SA on any of your CPUs ?
 
tibcsi0407 schrieb:
This one tops out at 1.23V, any higher makes trouble.
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Thats great, well its not but its fun to test something then.
Whenever you are not working.
1716972316934.png

Also this is insane , haha.
Be careful - at 300mV drop (due to under-/overshoot), PMIC and supply design might reach a limit.
According to specifications it will.

At this point of time, you may explore VPP_MEM pushing (skewing) slightly, for IC stability.
Else i see no issue to not run ~1.65 VDD_MEM :-)

Do you want to try and insta crash the system with:

SA 1300mV
VDD2_CPU 1400mV (if no boot 1380)
VDDQ_IMC 1335 (else 1330)

Same mem voltage.

I'm curious about something :d
(and i wonder if board will adapt RTTs with that drastic change)
 
Veii schrieb:
I understand, but the problem is, laws of physics is unforgiving.
And you have too many variables already.
If we don't hold to protocol, what are we testing or doing here :-)
Zum Vergrößern anklicken....
I stopped at 52 min when i got the screenshot cause you said 45-90 min...
Want me to rerun for 90 mins or try something else?
 
Darkthrone schrieb:
I stopped at 52 min when i got the screenshot cause you said 45-90 min...
Want me to rerun for 90 mins or try something else?
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Its perfect :)
Just explaining~

Darkthrone schrieb:
EDIT: Here is the 50 min run i promised...

I only changed SA from 1.14 i had yesterday, cause it failed on the first loop today (damn DDR5), to 1.135
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Haha
Thank youu
1716973378397.png

Now its behaving rather.
mm mm, ddr5 is fun, isnt it :d

Sorry i lost them, and this forum makes user-post lookup difficult
What was that V/F curve of your sample.
Seem to sweetspot SA here at 1.135 VID.

Ok next change
Im not sure if those are Class V A-dies, or they are old enough to be high binned ClassA

But please input:
RTT_WR 48,
NOM both to 80,
RTT_PARK to 40,
PARK_DQS to 48

That can run y-cruncher for 5 loops
And can run full TM5 suite
That should be then fine as your full baseline

I hope it passes else needs RTT_PARK & DQS change.
But voltages are just where they should be :)
Attached old VirusReport-Free TM5 which's changes were not closed-source
It still is P/E-Cores aware. new one is just a GUI + who knows what changes.
 

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  • TM5_0.12.3_1usmus25-CoolCMD.zip
    25 KB · Aufrufe: 31
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