[Sammelthread] Intel DDR5 RAM OC Thread

[snakeeyes]

PLL Terminations ändern die min/max voltage range.
Nicht über 0°C zu empfehlen

Er hat sie von 1.05 auf 1.1 angehoben.
Ich sehe da überhaupt kein Problem drin, wenn man in diesem Bereich bleibt und nicht noch weiter wild anhebt.

 

[X909]

Welche VDD, es gibt 3.

Zu hohe VDD(Q)_CPU, ja.
Zu hohe VDD(2)_IMC , fast nein. Data Rail.
Zu hohe VDD_MEM , nein. DRAM kann nicht degraden, nur die Gold Fingers charren/anbrennen welches du reinigen kannst.

Genau die Einschätzung meinte ich. VDDQ TX (CPU) ist unter 1.3V bei mir, easy. VDD_MEM interessiert mich nicht, da memory eh nicht degraded und selbst wenn würde ich das in Kauf nehmen.

VDD2_IMC / MC auf ASUS Boards? Wie hoch ist Spec volt da? Gibts ein DDR4 Äyquivalent? Kann man da sicher über 1.4, 1.5V gehen oder fackelt dann was ab?

 

[Veii]

@X909
VDD(2)_MC kann die 1.6v-1.62 halten.
Ob es langzeitlich sicher ist, kann dir leider keiner sagen.
Es ist eine Data Rail. Nach einer Range stürtzt es einfach ab.
Das selbe mit SA.
Manche können die 1.24 nicht halten andere kommen bis 1.35v.

VDD(Q)_CPU, bewegt sich bis etwa 1.4v
Aber bei beiden Spannungen ist der Voltage Wert egal.
Es wird (A)mperage matching gemacht.
// Wie "effektiv" diese Spannung nun ist, hängt von vielen Faktoren ab.
// Einer davon ist PLL ein anderer die (proc)ODT.
// Bzw die anderen versteckten ODTs & TermImpedances.
// (DQ, DQS, CK, CA, CS, VREF, MEM side 2... Usw)

Mit PLL beinflusst du diese Range und die Effektivität der Spannungen.
Ich würde es nicht benützen, da die Spannungen welche du siehst nur ein Bruchteil sind welche man anpasst.
Du machst dir mehr Probleme damit als Hilfe.

Sollte nur auf sehr schlechten Boards oder SubZero verwendet werden.
Der Unterschied ist groß, auch bei "nur" 50mV
Wie bei SA ein 10mV schritt schon "groß" ist

 

[tibcsi0407]

This is interesting:

https://videocardz.com/newz/msi-shows-off-z790-motherboard-with-compact-ddr5-camm2-module

 

[CarSalesman]

Er hat sie von 1.05 auf 1.1 angehoben.
Ich sehe da überhaupt kein Problem drin, wenn man in diesem Bereich bleibt und nicht noch weiter wild anhebt.

I've played with this voltage and it clearly does make a difference to the DDR5 environment, but it certainly hasn't been a miracle fix and I've since returned it to AUTO.

 

[Darkthrone]

After spending so much time trying to get 8000 stable, I tested each dimm on each slot alone.
One dimm on each slot at 8000c36
VDD/VDDQ 1.47/1.41 (1.45/1.40 also TM5 stable)
SAT 1.20 (bios value)
TX1.29 (bios value)
MC 1.4125 (bios value)
VDDQ training off/MRC fast boot off/fast boot off

One dimm pass 2 full loops of VST/VT3 on both slots.
Second dimm fail instantly on first slot (closest to cpu) and pass 2 full loops on second slot. So I keep that in the second slot and put the other dimm in the first slot.
Reboot with both dimms and it fail immediately.
So what is my issue now? Bad dim?

Tried to clear CMOS and start again, VDD/VDDQ 1.45/1.40, SA 1.15-1.22, TX 1.20-1.32, MC 1.35-1.45
Tried Pull-Up/Down 48-40/40-48
Ctl0DqVrefUP/DOWN 170/88

Nothing seems to work. Max I could get was 1 full loop of VST/VT3. TM5 Usmus is stable for a quick 6 loops.

 

[Veii]

@Darkthrone
You need to consider that plugged dimms create a load.
Disabling both MC-Links per "channel", slot ~ is how you test slots.
Removing one dimm changes load.

RON messing is no magical resolve
Neither are the values working for all scenario's.
Its specific to the encore @ strong ODT (low SA)

No test has any weight if bellow 45-90min.
EDIT:
Also there are multiple revisions of the same SKU
multiple apex and likely different encores.
Soo those values will differ.

---

@tibcsi0407 & @CarSalesman
Did you manage to make progress on SAGV and VRMAX ?

 

[tibcsi0407]

Did you manage to make progress on SAGV and VRMAX ?

I am struggling with something else.
When I flooded my top slot I was able to revive it, but seems like it degraded my memory channel somehow, maybe some short circuit or something.
Tried to clean slots, reseat the CPU etc, but my top slot could run only on 8200 max, for the bottom one 8600 wasn't an issue.

So today I installed my good old KF back to find out is it my board, or the CPU, but seems like it's the KS..
The KF was able to run with some fast settings 8 minutes Y on 8800 (on air) in the "bad" slot, so seems like the KS damaged somehow..
Shit happens.
I made a deep cleaning to the CPU cleaned every SMD and contacts, will retest it again later.
Also thinking on to put back my MC SP 90 13900 KS in the slot and see how it performs in the Encore.

 

[Veii]

Its very hard to believe you could @tibcsi0407
Due to send power towards slots always ending to ground, its waste.
Its bi directional, but still hard to believe.
Most end at VSS.

I wonder really
But even if you flood the 24pin
It would force a PSU off and at worse take that away. But even here, the PSU will protect itself from such "single cable" short

I would reconsider and to inspect the backside of the board
If anything looks corroded or burned.

Due to what i understand so far, this is very difficult and close to impossible due to ground amount
On Mainboard and on cpu pins.
Especially by how many parts have a protection against this scenario.
// or there is something i dont understand so far on design

Do you know if it flood it mid operation or on startup??

Edit:
The chance is much much higher for it to be just a training variable that let you run high clock on first plug-in.
You would have to flud specific rails (backside mostly) plus pcb coating be damaged , for this to have a chance to get back towards the cpu.
// and even then its effect is mitigated, or i should say "tamed"

Beitrag automatisch zusammengeführt: 27.05.2024

For example, its horrible and i dont recommend anybody to do this
But you can remove or plug in ram sticks in a powered state.
It hates it but it wont exactly fry it. Because it doesnt work like that
For example, this silly example also has protections against it, tho dont count on it.

I had to do this couple of times when you SPD corrupt one dimm,
but the system doesnt want to pass a boot check with it plugged (sodimm or udimm)
~ yet you need it plugged in order to flash it repaired. It was an init/timing scenario

Things just dont work that way
Else atmosphere between pins and housing/shell on the board
would most definitely condensate on XOC and cause the same you describe.
Exception here "variable" is conductivity rating on waterdroplets @ basically zero °C.
And filling the slot with vasiline will mess with ramOC strongly.

But ya the point stays ~ things don't work that way 🤭

 

[tibcsi0407]

Its very hard to believe you could @tibcsi0407
Due to send power towards slots always ending to ground, its waste.
Its bi directional, but still hard to believe.
Most end at VSS.

I wonder really
But even if you flood the 24pin
It would force a PSU off and at worse take that away. But even here, the PSU will protect itself from such "single cable" short

I would reconsider and to inspect the backside of the board
If anything looks corroded or burned.

Due to what i understand so far, this is very difficult and close to impossible due to ground amount
On Mainboard and on cpu pins.
Especially by how many parts have a protection against this scenario.
// or there is something i dont understand so far on design

Do you know if it flood it mid operation or on startup??

Edit:
The chance is much much higher for it to be just a training variable that let you run high clock on first plug-in.
You would have to flud specific rails (backside mostly) plus pcb coating be damaged , for this to have a chance to get back towards the cpu.
// and even then its effect is mitigated, or i should say "tamed"

Beitrag automatisch zusammengeführt: 27.05.2024

For example, its horrible and i dont recommend anybody to do this
But you can remove or plug in ram sticks in a powered state.
It hates it but it wont exactly fry it. Because it doesnt work like that
For example, this silly example also has protections against it, tho dont count on it.

I had to do this couple of times when you SPD corrupt one dimm,
but the system doesnt want to pass a boot check with it plugged (sodimm or udimm)
~ yet you need it plugged in order to flash it repaired. It was an init/timing scenario

Things just dont work that way
Else atmosphere between pins and housing/shell on the board
would most definitely condensate on XOC and cause the same you describe.
Exception here "variable" is conductivity rating on waterdroplets @ subzero.
And filling the slot with vasiline will mess with ramOC strongly.

But ya the point stays ~ things don't work that way 🤭

I don't think it's the board, since the KF was able to do 8800 in the slot where the KS could only 8200.
I've tried everything, CMOS reset, remove battery, BIOS reflash, BIOS switch, reseating, differenct CPU block, different dimms.

Only the different CPU helped. So I can say it can only be the CPU which got a minor damage in IMC part. Still can run 8200, which is not bad, but hey, it was better..
A minor Voltage jump can kill it, so I don't know, maybe it got a small shock.
It happened during the boot actually.

On 8400 in Y and TM5 insta kick me out, no matter what I set.
Just put in the KF and it was like plug and play...

 

[Veii]

It happened during the boot actually.

Then i can believe it to be a bigger shock.
In a running state this would have been fine.

Dimms can take 2.1-2.2v before going into flames
CPU technically can take a lot too, but for a short time
Training have protections

Just put in the KF and it was like plug and play...

Yea first training is somewhy full , always after a bios reflash.
Its better training for some reason, longer duration too.

 

[tibcsi0407]

Then i can believe it to be a bigger shock.
In a running state this would have been fine.

Dimms can take 2.1-2.2v before going into flames
CPU technically can take a lot too, but for a short time
Training have protections


Yea first training is somewhy full , always after a bios reflash.
Its better training for some reason, longer duration too.

Yes, even if you put the same cpu back it will retrain everything according to the seating in the socket.

I will try the KS again tomorrow morning. But I am afraid it won't come back.
Actually CPU part had no issue, it worked like charm on the same Vcore as before.

Things like this happen when you "play" too much with tha hardware. I can only blame myself, but tbh I never liked thic CPU.
Maybe I will buy a prebinned one and see how it performs.

 

[Veii]

Actually CPU part had no issue, it worked like charm on the same Vcore as before.

Alone if you continue with this theory, several IP blocks would have damage
i cant believe.

One of them is RingClk instabillity.

 

[tibcsi0407]

Alone if you continue with this theory, several IP blocks would have damage
i cant believe.

One of them is RingClk instabillity.

I loaded the Intel default profile too. SFT worked like charm. And also, 8200 worked like charm, even on C34. (maybe that was the problem, haha )

 

[Veii]

If one MC block got some damage, maybe you need to reconsider the RONs
Funny thing Madness hit 8800 on the Z790i lightning (+ y-cruncher) , on same RONs
Maybe there are magical indeed

 

[tibcsi0407]

If one MC block got some damage, maybe you need to reconsider the RONs
Funny thing Madness hit 8800 on the Z790i lightning (+ y-cruncher) , on same RONs
Maybe there are magical indeed

I don't know if it would help. I tried with manual RON's (with the 48/40-40/48) and with auto. No difference.
The error is instant in Y, like when you have not enough SA or VDD2.
I was thinking, if my board would be damaged, I would buy a Tachyon X to challenge a little.

 

[Veii]

I was thinking, if my board would be damaged, I would buy a Tachyon X to challenge a little.

Funnily the Z790i lightning gets better results than the Tachyon : ')
Tachyon owner need to work harder~~

You can go the path of least expensive, if you want
vs the most expensive one
I'm sure you'll learn valuable things, when struggling with low price boards and having to do bios mods.
Its at the end not boards fault.

EDIT:
There is an (old), new company on the block that might want bit modding touches
But runs a great pcb design ~ for low prices.
Could be fun to explore when we get no more freedom the biggest Boardpartner.

 

[tibcsi0407]

Funnily the Z790i lightning gets better results than the Tachyon : ')
Tachyon owner need to work harder~~

You can go the path of least expensive, if you want
vs the most expensive one
I'm sure you'll learn valuable things, when struggling with low price boards and having to do bios mods.
Its at the end not boards fault.

Yes, that little board is the GOAT, but I have 4 NVME SSD's, so it's a no go for me.
Saw Tachyon X on a pretty good price, it's around 600 Euros (with VAT) at some shops.
The only thing I don't like it's the E-ATX factor.

Are the Skews exposed in their BIOS? I had Z690 Ultra, but I don't remember unfortunately.

 

[Veii]

Are the Skews exposed in their BIOS? I had Z690 Ultra, but I don't remember unfortunately.

Uhh i dont remember
i have to ask a friend with the tachyon or dissect the rom.
// The X series is just an improvement on the HW side, with a tiny visual change on the ROM side & security change (both at the same time).

you got RTTs and you got RX-DFU presets
I am not sure about slopes.
RON exists, gladly now on ASRock's Boards too
// EDIT: the biggest change on Giga boards is, that things either train or they dont post at all.
// Bad VDDQ penality, is harsh. Its always no post.
// Unlike with ASUS boards where many things can try to get stable for some duration and get useful on XOC


On ASUS we have 35% visibility of stuff (https://www.hardwareluxx.de/community/threads/intel-ddr5-ram-oc-thread.1306827/post-30390693 oh its gone already)
On ASRock we have 25? % of it, but the important ones
On MSI and Giga we have 20%? of it.

Generally we are blind, "we" the normal consumers.
Soo what are +/- 5% if tuning is good, its fine
~ well for me its not, as i'm not an "overclocker" anymore, but you talk against a wall here

In reality close to nobody bothers, else such loss of options wouldn't be tolerated.
In reality people want a functional bios, without much technical explanation of the complicated things.
Thats all majority cares about , and a boardpartner that gives a good warranty policy + doesn't take more than 48h to answer.

 

[tibcsi0407]

Uhh i dont remember
i have to ask a friend with the tachyon or dissect the rom.
// The X series is just an improvement on the HW side, with a tiny visual change on the ROM side & security change (both at the same time).

you got RTTs and you got RX-DFU presets
I am not sure about slopes.
RON exists, gladly now on ASRock's Boards too
// EDIT: the biggest change on Giga boards is, that things either train or they dont post at all.
// Bad VDDQ penality, is harsh. Its always no post.
// Unlike with ASUS boards where many things can try to get stable for some duration and get useful on XOC


On ASUS we have 35% visibility of stuff (https://www.hardwareluxx.de/community/threads/intel-ddr5-ram-oc-thread.1306827/post-30390693 oh its gone already)
On ASRock we have 25? % of it, but the important ones
On MSI and Giga we have 20%? of it.

Generally we are blind, "we" the normal consumers.
Soo what are +/- 5% if tuning is good, its fine
~ well for me its not, as i'm not an "overclocker" anymore, but you talk against a wall here

In reality close to nobody bothers, else such loss of options wouldn't be tolerated.
In reality people want a functional bios, without much technical explanation of the complicated things.
Thats all majority cares about , and a boardpartner that gives a good warranty policy + doesn't take more than 48h to answer.

It's not easy. I can just hope that on next gen Asrock will continue from here where they are now with the Z790i lightning.
Saw the new Epyc AM5 CPU's. They are quite good actually from my point of view.

 

[Veii]

Saw the new Epyc AM5 CPU's. They are quite good actually from my point of view.

Yea improved IF, X series has 3D cache, hopefully dual CCD cache
may be great as an AI / compute cpu

completely new design
The APUs are fun for sure.
But you lack bios options freedom.

At least on the Server environment, you have more access.
Wish it was RDIMM tho . . .
Real dualrank would be great feeding the huge cache.

Beitrag automatisch zusammengeführt: 27.05.2024

It's not easy

I mean its not hard at all
But its hard dealing with higher ppl then~~

 

[CarSalesman]

@tibcsi0407 & @CarSalesman
Did you manage to make progress on SAGV and VRMAX ?

I got 8400c34 to run 2.5hrs of VST/VT3 in 20second iterations before error, RxDfe off. Becareful24 told me that's as good as it gets without debug menu.

SA 1.20, VDD2 1.425, TX 1.225, VDDQ_mem 1.42, VDD_mem 1.60, ParkDQS 60, CMD/CTL Drive Strength Up/Dn 2D [Disabled], CMD CTL CLK Slew Rate [Disabled], CMD/CTL DS & E 2D [Disabled]. This is text dump to BIOS settings: https://www.overclock.net/posts/29332691/

Don't know if you saw my post in ASUS Z790 thread on OCN. The BIOS yeeted Vcore to 1.72 despite having VRMax at 1.500. https://www.overclock.net/posts/29332253/

It isn't occurring anymore since I got it stable, but it seems like the DDR5 environment crashing caused everything to go haywire.

Now I'm on to 8600 but I think it is beyond the capabilities of this IMC.

Beitrag automatisch zusammengeführt: 28.05.2024

// EDIT: the biggest change on Giga boards is, that things either train or they dont post at all.
// Bad VDDQ penality, is harsh. Its always no post.

I prefer this type of behavior. Z790 Kingpin is this way. Saves times and prevents mistaken hopefulness.

 

[Veii]

I got 8400c34 to run 2.5hrs of VST/VT3 in 20second iterations before error, RxDfe off. Becareful24 told me that's as good as it gets without debug menu.

You chose to accept defeat ?

Checked your OCN post, i see how things are.
This would explain in who's mind "CMD/CTL DS & E 2D [Disabled]" ~ idea was.

Don't know if you saw my post in ASUS Z790 thread on OCN. The BIOS yeeted Vcore to 1.72 despite having VRMax at 1.500. https://www.overclock.net/posts/29332253/

mmmmm
This may happen due to PPP and PT4 like Igorslab explained.
It is scary tho. The throttle basically means that it was not a fake readout and behaved exactly as it should.
// which is how it should be, if boardpartners get their ICCMAX, Curve and VRMAX together. PT4 and TDC included;
In non listening scenario's, you might have a dead cpu or strongly degraded by now. Ty for listening~

EDIT:
To assure you more, those spikes and insta kills usually happen on training not mid load.
Some sensor must have had crashed for this to happen, although its embarrassing (not for you) that this exists.
Reminds me of the GENE and blobbed AM5 substrates, where we kept hiding boosting behavior in a bios.
And later removed diesense tracking , as it was showing that the issue-indicator remained active and overshooting
... in a bios state, where boosting should not be allowed , where i'm sure AMD didnt change their mind on this
Probably really related to PT4 limit not following ICCMAX (slightly over it), but who knows - has those vibes again

Now I'm on to 8600 but I think it is beyond the capabilities of this IMC.

I think no.
But not one IP Block

Good timezone

ParkDQS 60,

Why

 

[CarSalesman]

You chose to accept defeat ?

Checked your OCN post, i see how things are.
This would explain in who's mind "CMD/CTL DS & E 2D [Disabled]" ~ idea was.

I was advised this is success.

CMD/CTL DS & E 2D [Disabled] <----my idea, along with CMD/CTL Drive Strength Up/Dn 2D [Disabled], and CMD CTL CLK Slew Rate [Disabled]

What do you advise if I have CTL0's set but everything else on AUTO? Should I:

1. Set everything manually?

2. Re-enable one or more of the three of the trainings?

 

[Veii]

CMD/CTL DS & E 2D [Disabled] <----my idea, along with CMD/CTL Drive Strength Up/Dn 2D [Disabled], and CMD CTL CLK Slew Rate [Disabled]

Here you have three things
Basic signal, signal drive+filter, signal phase+speed
You combine all 3 , to cover just one category change on signal alignment.
They are different things, slopes are not the resolve to everything. How its feed matters , not the opposite.
Not 100% confident on "E" meaning.

Then we have

*Official* Intel DDR5 OC and 24/7 daily Memory Stability...

www.overclock.net

Using logic alone.

Your defined margins due to CTL0, aka your [Redacted] suggestions given by helper
Cause you no favor.
A point of a good VREF is a high margin.
You achieved the opposite by the person focusing soo much on pin-point stability, without factoring variance.
Your tuned values which they seems started to remake a 3rd time, probably just so they are different and can be "their own" again

Caused a limitation of margins, not an increase.
I advice to rethink that path & if corresponding researcher also reads that~~
Rethink the outcome by logic

If its indifferentiable to ASUS "high binned" tuning scenario (old),
How do we differentiate it again like what was the achievement here.

We need more margins not less margins 🤭
And the least we need, is confidential data.
I don't know~

See , blurring s*kks
Just a reminder that we go nowhere with this proprietary mentality.
And especially if researcher spends soo much lifetime for himself, just to keep things secret.

What do you advise if I have CTL0's set but everything else on AUTO? Should I:

CTL1+CTL2 are different from CTL0.
If you+helper mess with CTL1+2, they mess with training delay and RTT.
If X messes with VPP, they mess with the same ~ training delay, voltage strength, and phase alignment
Falling into the same rabbit hole you are right now ~ inconsistent thermal variance and bad thermal stability.

Remember i push you to 100° y-cruncher stable ~ early days

Advice,
Probably dont bother.
You put your focus on the wrong path.
Especially as CTL0 ODT is sample unique, and here even by logic ~ will never be SA scaling.
Nor will be board to board or cpu to cpu replicable.
I don't know~

Beitrag automatisch zusammengeführt: 28.05.2024

EDIT:
Given i remember this person and their way of work
I think they've fallen into the trap of learning from ASUS (rutool, hex) work and matching Down's as a flat thing.
This only functions if Board is build perfect, and even then, you can't just put a DOWN baseline and expect it to work

There are far too many outer factors, that prevent such a book-like perfect scenario (of tuning)
Book-like "perfect" tuning scenario only works @ the lab and design stage.
Yet even that will not guarantee perfect outcome without variance.

Soo even if lets say "i" was PCB designer and all checks pass.
They will never be identical in outcome past design and past silk step.

Now adding CPU variance and dynamic ODT to this topic.
You simply can not run them at the same duration and same endpoint.
That is for all that make DQ and all that make DQS.
Training exists because its required.

I think researcher fell into this rabbit hole.
Remembering old talk and seeing concurrent outcome (bad margins)

 

[Darkthrone]

@Darkthrone
You need to consider that plugged dimms create a load.
Disabling both MC-Links per "channel", slot ~ is how you test slots.
Removing one dimm changes load.

Tested as you suggested. Both dimms installed. Each disabled through bios.

SlotA Enabled/SlotB Disabled

SlotA Disabled/SlotB Enabled

SlotA+B Enabled

 

[Veii]

Tested as you suggested. Both dimms installed. Each disabled through bios.

Funny that slot B has lower bandwidth, slightly.
This sounds like a ring issue tbh. Can you export me the Bios config ?

Do you pass 2-3 rounds of CB15 Extreme (benchmate) ?
Without it crashing ?

 

[tibcsi0407]

Funny that slot B has lower bandwidth, slightly.
This sounds like a ring issue tbh. Can you export me the Bios config ?

Do you pass 2-3 rounds of CB15 Extreme (benchmate) ?
Without it crashing ?

For me it's strange that his IVR TX dropping below 1V. Something strange happens on that rail.
My IVR TX only dropping some mV below the set value.

In my opinion SA is too much too (1,12V should be enough for 8000). TX seem also too much for that memVDDQ.

 

[Veii]

For me it's strange that his IVR TX dropping below 1V. Something strange happens on that rail.
My IVR TX only dropping some mV below the set value.

Mm mm
It can be due to powerlimiters or due to instability.
Its a dynamic voltage at the end

 

[tibcsi0407]

Mm mm
It can be due to powerlimiters or due to instability.
Its a dynamic voltage at the end

Never saw it dropping that huge. Even on very unstable environment it stays around the set value.
Look at his two per channel test above, both stays around 1.32V.