Ahhhhh
Now i get it
@CarSalesman @RedF @Wolf87
Soo outside of DDR4 support in FW
For 2H(eight) and 4H 3DS dimms
That is 128-256GB Dimms
RRD_SameLogicRank = 4
tFAW_SamelogicRank = 16
Still at CCDS 8 as roundtrip while 512 bytes per logical rank
For 1kb pagesize
RRD_S (1KB) minimum 8
RRD_S (2KB) minimum 8
tFAW (1KB) target 32
tFAW (2KB) target 40
its 1 & 1/2th loops of strobes for 2kb pagesize on 1H dimms (all UDIMM).
Now only thing to figure out
Is Subchannel layout on IMC-Ctrl with 4 logical ranks or 2 (on 2 single sided dimms)
Because effectively if CPU-Vendor wants.
And we run all as 512bytes pagesize with two MC links. Intel runs dual channel per dimm, might be 512b by default.
We can effectively half RAS to RAS and FAW on per subchannel ~ without affecting roundtrip limit of 8 or any other CCD_X timing.
If we force (AMD) 2KB Pagesize
our RRD_X 8-8 runs in BL32 OTF mode.
Instead BL16 with BC8 OFT mode.
I'm a bit confused why consumer should have RDIMM 3DS support
Especially because UDIMM doesnt allow 2H layouts to my understanding. Tho SKU would allow in correct server board RDIMM support,, if i'm not mistaken
Hence the relevance of most DR timings is irrelevant ?
But given minimum FAW on AMD is 20 not 16 (Vendorlimit, 16 should be min) ~ they may actually have that in mind.
As IMC FW is not really OTA updateable without a new SKU. It can but is a huge security risk.
Guess you guys can dig and figure out, how much logical ranks (together)
Your system runs on default state to decide if any timing bellow 1KB Pagesize makes sense.
This also changes RAS target ~ which already is not exactly correct at RCD+RTP. As Cmds with AP exist too.
And RCD+RTP+X , X is pagesize target.
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