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Ram-Mogul
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Hier noch Auszüge aus dem OC.net, die wichtig fürs OC sein könnten und sich auch 1:1 mit meinen Erfahrungen decken. Als Beispiel: Wenn ihr ein RAM Setting nicht gebootet bekommt, könntet ihr zuerst mal den RING-Clock senken. Ich bin mir nicht mehr sicher ob mein aktuelles Setup 100% stabil ist. GSAT wirft nämlich ab und an mal errors. Bin da noch dran das auszuloten. Mit der SA traue ich mich aber für 24/7 nicht deutlich über 1,4v zu gehen.
1) Disabling all E-cores will give you higher maximum clocks (usually at least +1 bin) on the P-cores. P cores also have access to the full L3 cache if E cores are disabled.
2) Also, disabling all E-cores allows you to yeet the ring ratio. Ring can go up to x50 if E-cores are disabled. With E-cores enabled, you are not going to get much higher than x42 to x44.
3) There is some strange relationship between the ring (cache) and the E-cores. If you overclock the cache too high with the E-cores enabled (e.g. 44+), you may encounter BSOD’s that look identical to “memory instability” errors (e.g. “Memory Management, IRQL_NOT_LESS_OR_EQUAL”. This is beyond me. CSTKL1 is the one to refer to with these.
4) There is also some sort of relationship between the E-cores and memory overclocking as well when pushing high memory clocks possibly with respect to the Atom L2 cluster 0 and cluster 1 voltages.
5) For every E core that is enabled, you seem to need about ~7mv more voltage for stability. So all 8 e-cores enabled seem to need about 56mv (0.056v) higher vcore. Might be the E-cores are siphoning power from the P-core supply.
6) For every small core enabled, you lose about an estimated ~15.85 MHz in P-core fully loaded frequency. So for all E-cores enabled (vs them all disabled), expect about -120 MHz off your max fully loaded clocks compared to all E-cores disabled.
7) VMAXSTRESS seems to not be supported on this platform. You can use VR Voltage Limit (mv) to limit your target load voltage (before vdroop) when using adaptive voltage modes.
8) Thermal limits may be hit around 1.3v die sense voltage and >210 amps of current. Maximus boards can monitor CPU Current (Amps) in EC in HWinfo64 (newest version) or on OLED (Maximus Extreme).
9) There are THREE SP ratings. One for P-cores, one for E-cores and the global SP. You can see them in Asus AI settings. I am uncertain how the global SP rating is affected by this.
CPU Input Voltage (VCCIN AUX), external default value 1.8v rail, feeds the FIVR. Don’t care about this unless LN2.
CPU 1.8v small rail, external, default value 1.8v, may feed PHY/PCIE, don’t bother.
CPU Vcore. FIVR rail type, uses SVID for default, feeds big+little, important to care about.
CPU GFX, external SVID, feeds GT, care about if you’re using the iGPU.
CPU VCCSA system agent, SA VID for “set”, IVR VCCSA for “get”, FIVR rail type, default value based on SVID, care about it for memory OC.
Memory Controller voltage, IMC VDD, external 1.1v rail, feeds another part of mem controller, care about it for memory OC.
IVR Transmitter VDDQ, VDDQ TX Voltage for “Set”, IVR TXVDDQ for get, FIVR rail, 1.1v default value, voltage level for the transmitter part. Important for memory OC
PLL Termination Voltage (VTT), external 1.05v default rail, Sustain and “Sustain gated” rail, only care about this for LN2 OC.
CPU Standby Voltage, external 1.05v rail, sustain/gated, only care for LN2 OC.
IVR VCCIO Analog: ignore this.
IVR Atom L2 Cluster 0, Atom L2 cache cluster 0, need for LN2, effect is undermined for regular OC, may or may not affect Cache OC with E cores enabled, or MEM OC. Cstkl1 knows more about this.
IVR Atom L2 Cluster 1: same
PCH: 1.05v external rail, primary core voltage, no need to care about this
PCH 0.82v rail: primary “Well(?)” voltage, ignore this.