According to AMDs presentation of RDNA 1 & 2 (read now a bit into it but still not enough)
After a certain frequency region ~ L3 + 128mb infinity cache *, starts to be the bottleneck in how fast & effective data can even reach the compute cores.
* this is the main difference between batches and it was expected that lower tier versions lower this cache for cost saving measures, as they don't need it on a low buswidth, when cores can not boost high
** also the reason AMD doesn't need to use 256 or 384bit wide bus (that costs a lot ~ NVIDIA and draws too much power)
Which also goes for passing through RT accelerators
SOC seems at 1000-1200 to not affect much about it, as Infinity Cache is still "too slow" to handle effective frequency beyond 2600 ~ at it's 2200 Freq
(something before/after it throttles high FCLK shining through)
Near 2600 core, it requires by AMD defined 1940Mhz Infinity Cache Freq ~ and according to them "the more load you put on it, the faster it gets as frequency straps max out, soo transfer happens faster"
Which also means
That after a certain point, FCLK does affect negatively Vclk + Dclk is required to be pushed
Vclk pushing seems to fail quite fast on GT2 with a hangup/crash (no artifacts) , while Dclk is not 100% clear as of now but does artifact
I was silent for a bit till i have a proper scale, but it's funny ~ as you run nearly perfectly identical settings to me
@Sylwester.
Just the difference that i try to understand the power tables, while you go all in ^^
We'll get this soon, but test please PhyClk range, just be cautious with min frequency on SOC
As when this one is too high, it messes up boosting straps (gear shifting)
(970 Phyclk was the max i could push before it started to autocorrect throttle)