[Sammelthread] Intel DDR5 RAM OC Thread

[tibcsi0407]

Doch hatte ich
Yay !

Those are RTT issues
Yep, powering is f*iretrucked. Indeed.
8600+ is f**iretrucked. Not IMC issue.

Manual mode it is
Let me get home on pc and ill build something for you.

IN-MEM delta scales till 105mV
Without issues.
60mV is guaranteed to work.
100mV should be easy unless powering is f**unctionaly broken.

Thank you, I will run the higher VDD in the meantime. ☺️

 

[Veii]

Alright,
@tibcsi0407 what is the current current state.
I think i found your issue

It is timings and RTT related.
Confident~

Error is past write pre read.
To make sure
Do we still use RX-DFE or the plan was to revert back without DFE on DIMM and to kill off error #4 ?

EDIT:
Error to 89% is DQ related + timings are too tight.
Potentially CS but more unlikely
Its not DQS or CLK related.

Its not VDDQ related, although the different kind of errors for In-Mem delta's make little worry.
We likely have two issues, outside of just two timings.
Its issue between bankgroup jumps, thats for sure ~ but those go hand in hand with RTT issues.
So no wonder it reports me RTT issues non stop.

 

[tibcsi0407]

Alright,
@tibcsi0407 what is the current current state.
I think I found your issue

It is timing and RTT related.
Confident~

Error is past write before read.
To make sure
Do we still use RX-DFE or the plan was to revert back without DFE on DIMM and to kill off error #4 ?

EDIT:
Error to 89% is DQ related + timings are too tight.
Potentially CS but more unlikely
It's not DQS or CLK related.

Its not VDDQ related, although the different kind of errors for In-Mem delta's make little worry.
We likely have two issues, outside of just two timings.
Its issue between bankgroup jumps, that's for sure ~ but those go hand in hand with RTT issues.

Now I am passed 18 cycles and still running with these settings:
TX: 1.35V
MC: 1.481V
VDD: 1.52V
VDDQ: 1.47V
SA: 1.22V

I didn't try this combination with this SA, but iit can still error out later, so we will see. 90 minutes line passed at least.
RX-DFE is still enabled

What would be your suggestion if we can do this one? (even if I pass this, Y will be a different story. )

Bios is 0081 now. I don't think it's any different from 0080, date is similar.


Update:

It passed.

Update:

Y failed in second round

 

[laychi]

Immer.
Geht tiefer aber momentan bist du nicht in der Situation eine stabile Baseline zu besitzen.
Generell hat es so zu bleiben wie es nun mal ist
Der Rest sind transition timings. Timings ob hoch oder tief sind nur extras.
Man sollte sich nicht auf virtuelle Werte fokussieren, sondern so viel Clock wie möglich (ohne Throttling) rausholen.
Immerhin rennt jeder die Gear2 penalty.

Klingt gut.
Es kann sein dass VDDQ_CPU höher muss als 1.2.
Soweit geht die Rechnung jedoch auf.

SA auf 1v ist niedrig. aber soweit ok.
1.1-1.15 ist ein guter Wert, bloß vorerst wohl nicht nötig.

Minimum
Ein crash unter 15min ist zwar klar, aber es bleibt ein Problem bis minimum 90minuten.
Selbst dann hast du Möglichkeiten instabil zu sein, da man 2-6 Stunden y-cruncher VST+VT3 rennen sollte.
Error Correction macht seine Arbeit sehr gut. Aber ODECC ist ein Teil der Logik, somit kann man auch mit Korrektur leben.

Wenn man aber schon für sich die genauen Spannungen herausfinden möchte, muss es lange rennen.

Hi @Veii

Leider nicht gepasst. Mit tWR 66 und trefi 114687
tCWL hatte ich auch probiert 30 und 32 wie du es gesagt.
Dannach Ich habe erst probiert das VST/VT3 2 stunde zu lauffen lassen. Mehrmals fehler hatte ich bekommen, Ich habe probiert viele verschiedene einstellungen.
Erhöht die SA und VDDQtx, hatte fehler ohne ende. Dannach hatte ich noch das vcore erhöht und 2 stunde VST/VT3 geklappt.
TM5 usmus abgelaufen ohne fehler @P56 E45 R49 (und meine vorheriger gespeichert einstellung)

gleiche spannung einstellungen bei SA,VDD2,VDDQtx,DRAM aber das cpu takt hatte ich reduziert P55 E44 R48 Vcore 1,28V, dann es war nicht mehr gut., wieder fehler.
Natarlich ich habe probiert andern SA höher, niedriger spannung, bei VDDQtx auch, VDD2 Auro gelassen(~1,430V) Dram erhöht. Bringt aber leider gar nichts.

Ich versuche jeden tag mindestend einmal ändern die einstellungen und das TM5 lauffen lassen @P55 E44 R48, mit verschiedene einstellungen, aber er will nicht gut sein.

Idee?

Wegen hoch temperatur möchte ich nicht VST/VT3 @ P56 E45 R49 Vcore 1,33V lauffen lassen.

Zebra_hun hatte gesagt das die nächste sache was ich korrigieren muss(wenn das arbeitsspeicher wird stabil) ist das CPU einstellungen.V/F Curve soll ich benutzen.
Ich werde das auch schauen, aber die arbeitsspeicher macht gerade mir kopf kaputt
Wieso ist es gut P56 und nicht gut P55;...grrrr

 

[elita]

Du machst mir Patriot nichts falsch.

Benutzen die nicht sowieso alle die Hynix A bzw. M-Dice? Also GSkill, Corsair, Kingston und ich glaube Patriot, haben alle die Hynix-Speicher im Einsatz. Die unterscheiden sich vermutlich nur im Aufdruck und dem PMIC Dingens, den die da drauf machen.

 

[Veii]

Now I am passed 18 cycles and still running with these settings:
TX: 1.35V
MC: 1.481V
VDD: 1.52V
VDDQ: 1.47V
SA: 1.22V

I didn't try this combination with this SA, but iit can still error out later, so we will see.

RRDL 13
WTRS 7
WTRL 26

tWRRD_DG/SG AUTO

Update:

Y failed in second round

I don't like how many trickeries we have to use.
VPP for mem is 1.9
CPU 1P8 (AUX) is 1.9

Benutzen die nicht sowieso alle die Hynix A bzw. M-Dice?

Es gibt 3 , 24GB Dimm Hersteller.
Alles unter 7200MT/s "kann" nicht Hynix sein.

Idee?

Kein fixen clock, keine fixe Spannung.
400A ICCMAX

Vcore wird verteilt.
Dazu gehört der IMC.

 

[tibcsi0407]

RRDL13
WTRS 7
WTRL 26

tWRRD_DG/SG AUTO

What do you think, should I keep the current one or use your suggestions for Y stability?

 

[Veii]

What do you think, should I keep the current one or use your suggestions for Y stability?

Change it, because you need to scale up.
CTL0 can be used now.

There are many ways to fix it - but its not one issue.
Busy for tonight ?

TM5 is clear for now.
Needs to be re'checked tomorrow after a coldboot.
Especially when fixing RTTs

Check CTL0 progress, (y-cruncher) and check then AC_LL + 0.03 , progress.
Keep me up to date

 

[tibcsi0407]

Change it because you need to scale up.
CTL0 can be used now.

There are many ways to fix it - but its not one issue.
Busy for tonight?

TM5 is clear for now.
Needs to be re'checked tomorrow after a cold boot.
Especially when fixing RTTs

Check CTL0 progress, (y-cruncher) and check then AC_LL + 0.03 , progress.
Keep me up to date

Tonight can't check it, but tomorrow I will do that.
CTL 0 already fixed if you mean the Vrefup?

 

[Veii]

CTL 0 already fixed if you mean the Vrefup?

I remember you checked on 6400MT/s
But you scale up by clock.
At least DQ VREF.

It is incorrect to scale CTL1's per clock.
Not sure if you actually scaled up.

 

[tibcsi0407]

I remember you checked on 6400MT/s
But you scale up by clock.
At least DQ VREF.

It is incorrect to scale CTL1's per clock.
Not sure if you actually scaled up.

I have the values you suggested before. Maybe 182 up 100 down, but not sure.

 

[Veii]

I have the values you suggested before. Maybe 182 up 100 down, but not sure.

If 178-96 then its wrong
If 182-100 then its ok.

Sanity checking

 

[tibcsi0407]

If 178-96 then its wrong
If 182-100 then its ok.

Sanity checking

It's 182-100 ☺️ didn't even try without that.

 

[tibcsi0407]

Change it because you need to scale up.
CTL0 can be used now.

There are many ways to fix it - but its not one issue.
Busy for tonight?

TM5 is clear for now.
Needs to be re'checked tomorrow after a cold boot.
Especially when fixing RTTs

Check CTL0 progress, (y-cruncher) and check then AC_LL + 0.03 , progress.
Keep me up to date

They came back with the new timings too. I changed the aux in and VPP too.

Update.

Tried the old settings, this time lower MC 1.46V. Acc. to the cheat shet it's refresh related.
Need more Vdimm?-

 

[Veii]

They came back with the new timings too. I changed the aux in and VPP too.

Some bug had sneaked into the sheet
Reverted and fixed

1 = 0 was wrong,
A movement bug.

Unfortunately all still are RTT reports.
On the first attempt , what happens if you keep CPU_AUX

Keep DFE in any case.
Increase both mem LDOs +30mV.

And just retest ?
I think there is no way around touching RTTs at this clock and higher.
All issues have some root of "powering is bad, powerdown is bad, RTT or RRD/WTR is bad"

As long as you don't have zero's , we have a chance for 8600 onwards.

EDIT:
If you can get the debug menu back from CarSalesman or ask Safedisk for a compile.
That would also help. He may give you, with NDA to not share the bios.
// but then you work "with me" so you may not get it 🤭🤭
Else the option left is to use alternative tools, and doing hex changes, on corresponding fields.
^ for working with DFE and remain training options.

RTT for sure it is, but unsure if something more is behaving/predicted odd.

Beitrag automatisch zusammengeführt: 20.01.2024

Update.

Tried the old settings, this time lower MC 1.46V. Acc. to the cheat shet it's refresh related.
Need more Vdimm?-

Ah,
nono RRD and WTR increase is very likely a must
But neither that nor voltage will fix "RTT/Powering issue".

Voltage alone means nothing.
MC-Link can be stronger, but MC-Link is ok how it is ~ else you would have dropouts report.
Its not that either.

Its also not VDDQ.
Timings may be too tight but 13/26 is plenty.
WTR at 7 or 8 is basically no change. 2nd Write is delayed anyways and first happens at the 4th nCK.
If next is at 12 or 8 , not so important~.
Value can remain RRDS-1 or = RRDS. The WTRS value.

I dont think it makes too much sense to mess with VDDQ delta's
What may be the correct path is SA back down till you still pass minimum 1 cycle y-cruncher.
To verify there are no harddropouts, and DIMM ODT training off. To start working with RTTs

Thats likely the right path to take.
"better DFE" can fix this, given you are completely unstable without RX-DFE.
But that's not a luxury for consumers or prosumers. Unfortunately~

 

[tibcsi0407]

Some bug had sneaked into the sheet
Reverted and fixed
Anhang anzeigen 961671
1 = 0 was wrong,
A movement bug.

Unfortunately all still are RTT reports.
On the first attempt , what happens if you keep CPU_AUX

Keep DFE in any case.
Increase both mem LDOs +30mV.

And just retest ?
I think there is no way around touching RTTs at this clock and higher.
All issues have some root of "powering is bad, powerdown is bad, RTT or RRD/WTR is bad"

As long as you don't have zero's , we have a chance for 8600 onwards.

EDIT:
If you can get the debug menu back from CarSalesman or ask Safedisk for a compile.
That would also help. He may give you, with NDA to not share the bios.
// but then you work "with me" so you may not get it 🤭🤭
Else the option left is to use alternative tools, and doing hex changes, on corresponding fields.
^ for working with DFE and remain training options.

RTT for sure it is, but unsure if something more is behaving/predicted odd.

Thank you. Now I played with wtr a little, this time reduced WTRS.
I will retry it with your suggestions when its finished.

I played with RU tool but have no idea which lines should be changed. I will message to Carsalesman, maybe he would help.

I believe too that this can be catched. Won't be easy but maybe doable.

 

[Veii]

I believe too that this can be catched. Won't be easy but maybe doable.

Ya no,
You are completely unstable without DFE on DIMM.
I don't think that can be denied.
(For fun increase dimm voltage a bit on mem for both LDOs ~ on old profile + fix RRD and WTR)
and we may check how bad it is without RX-DFE

But it wouldn't surprise me.
DFE past 8000 (in best case scenario) is a requirement.
Usually even past 7400 but i got it to work without on 12th gen.

Spoiler: EDIT: ~ and with full access, its just silly / both channels [KLEVV]

Even AMD gives you access to both RX & TX DFE.
Its crucial. DFE per DIMM-PCB and Vendor will differ. Access is very much needed.
We'll see~

EDIT:
DFE "Training" part and similar write leveling training part, may misspredict at high clock
It is ok to not enable training, but also is not ok to have two options ~ preset or random training.
Users need access. Preset can never cover more than 2-3 DIMM-Vendors. Even if you split for X-Capacity.

For RU-Tool shenanigans, you want to enable "Publish Hll Resources"
To have higher chance making something out of "raw data".

 

[tibcsi0407]

Ya no,
You are completely unstable without DFE on DIMM.
I don't think that can be denied.
(For fun increase dimm voltage a bit on mem for both LDOs ~ on old profile + fix RRD and WTR)
and we may check how bad it is without RX-DFE

But it wouldn't surprise me.
DFE past 8000 (in best case scenario) is a requirement.
Usually even past 7400 but i got it to work without on 12th gen.

Spoiler: EDIT: ~ and with full access, its just silly / both channels [KLEVV]

Even AMD gives you access to both RX & TX DFE.
Its crucial. DFE per DIMM-PCB and Vendor will differ. Access is very much needed.
We'll see~

EDIT:
DFE "Training" part and similar write leveling training part, may misspredict at high clock
It is ok to not enable training, but also is not ok to have two options ~ preset or random training.
Users need access. Preset can never cover more than 2-3 DIMM-Vendors. Even if you split for X-Capacity.

For RU-Tool shenanigans, you want to enable "Publish Hll Resources"
To have higher chance making something out of "raw data".

I will check it without DFE in next round. Should I disable it or leave it on auto?

When you worked on the BIOS did you find out what's the difference between ASUS and standard training option?

Update:

1 error 13 on the very end:
Should be an RTT issue?

 

[Veii]

I will check it without DFE in next round. Should I disable it or leave it on auto?

When you worked on the BIOS did you find out what's the difference between ASUS and standard training option?

Unfortunately no.
I found where to look for, but not what to do with it.
Else i would be able to read out their tuning and predictions.

I did not focus time to dig on training options, but spend time doing my own
Because whatever trained before, wasn't well suited.
And time was limited.

Update:

1 error 13 on the very end:
Should be an RTT issue?

Lower REFI might fix that, but its tradeoffs again.
You are still on tight RRD_ and WTR_
Can you drop all _DR delays on 0.

And drop R2-R7 RTLs to 0
R0 & R1 should stay.

And as test/throw away profile

+ tWR as 28. *

* If you change WTR, please WR as 30

Beitrag automatisch zusammengeführt: 20.01.2024

I will check it without DFE in next round. Should I disable it or leave it on auto?

Auto is ok.
DIMM Vendor usually defines DFE on DIMM side.
I think enabled, overrides that to ASUS tuning.
Alternative option would be silly, as DFE is core requirement & IC/DIMM Vendor does provide that target.
Would mean ASUS ignores. I don't think thats the case. I think their preset override whatever was before.
Yet still no manual access for consumer, except random training or own preset. *

* Which again, can never fit for all DIMMs.
And if, that means targeting TX Tuning to this target.
Which is the reverse of what should be done. ~ i think
// Because Boardtuning is unique per PCB and different input require completely different values on RX.
// There is no way to get some sort of similarity, even if building ontop of IBIS preset. It never will be perfect on such approach.
Maybe i'm wrong 🤭

 

[tibcsi0407]

Unfortunately no.
I found where to look for, but not what to do with it.
Else i would be able to read out their tuning and predictions.

It never helped me, but who knows,aybe worth a try.

Beitrag automatisch zusammengeführt: 20.01.2024

And as test/throw away profile

+ tWR as 28. *

* If you change WTR, please WR as 30

These are already set. But twr is 24 now, I will raise it.

Beitrag automatisch zusammengeführt: 20.01.2024

Which again, can never fit for all DIMMs.
And if, that means targeting TX Tuning to this target.
Which is the reverse of what should be done. ~ i think
// Because Boardtuning is unique per PCB and different input require completely different values on RX.
// There is no way to get some sort of similarity, even if building ontop of IBIS preset. It never will be perfect on such approach.
Maybe i'm wrong 🤭

Should be true. I have Gskill 8000 kit, it's quite popular. Should be included.

I started a new test with 1.431V MC, I will try your suggestions in the next round. Maybe it helps on the training a little.
I am a little bit confused about this MC Voltage, it's always liked the high range but looks like the lower range fits too.
Edit

It was too low. Error 6 after 20 minutes.

 

[Veii]

These are already set. But twr is 24 now, I will raise it.

Testing
Dont think it will make a difference.
24 is "maybe too low", but it should be just ok.

You get "thermal issues + REFI issues" on 28° ~ its not thermal issues
Its just unhappy SI/SNR issues.
If no progress now and then you give me an Auto-DFE screenshot, to see if any other non RTT errors arrive.

Then we'll start with RTTs, because idk what else to find as side issue. Its just unhappy RTTs.
It's either RTT or CTL1 fixing. Last is just annoying~

You can skew bit with SA
You can skew bit with PLL to reach destination
But if you start now with bandaids, you wont reach further.

Beitrag automatisch zusammengeführt: 20.01.2024

It was too low. Error 6 after 20 minutes.

Yep.
Well if you really want to verify, increase AC_LL ~ see if lack of voltage supply on IMC
Or lack of supply past IMC.

MC VDD-Link (VDDIO) ≠ IMC voltage.

 

[tibcsi0407]

Testing
Dont think it will make a difference.
24 is "maybe too low", but it should be just ok.

Just set it and booted with auto DFE. I am really curious to see what happens.
Set RTL too, report back soon.

For RTT do you have idea where to start as a base?

 

[Veii]

For RTT do you have idea where to start as a base?

Its likely near

NOM RD ~ 80
NOM WR~ 80
WR ~ 60
PARK ~ 48
DQS ~ 40
On strong ODT

But on current ME FW and current changes
It might run
80-80-48-40-48
or
80-80-60-40-48

RTT_WR 40-48 is for 16gb dimms, (single sided)
48-60 is for 24gb dimms
60-90/120 is for 32gb (dual sided)
and if 80-90 ohm option exists, then its 120 for 48gb dimms (dual sided)

Dual sided may also run stronger RTT_NOM_WR (34-40ish) *
It very much depends.
SK Hynix and HJ OEM PCBs behave similar

Kingston, Teamgroup, V-Color, Corsair ~ behave similar (consumer tier)
Galax, Teamgroup ~ prosumer space behave different
ViperTW theirs behaves slightly different
And G.Skill ones behave completely different ~ from for example OEM PCB design.

---

EDIT:
* Single Sided dimms may go by without any RTT_NOM
But likely behave better with some NOM ~ WR is the key factor for NOM & PARK behavior.

 

[tibcsi0407]

Its likely near

NOM RD ~ 80
NOM WR~ 80
WR ~ 60
PARK ~ 48
DQS ~ 40
On strong ODT

But on current ME FW and current changes
It might run
80-80-48-40-48
or
80-80-60-40-48

RTT_WR 40-48 is for 16gb dimms, (single sided)
48-60 is for 24gb dimms
60-90/120 is for 32gb (dual sided)
and if 80-90 ohm option exists, then its 120 for 48gb didmms (dual sided)

Dual sided may also run stronger RTT_WR (34-40ish)
It very much depends.
SK Hynix and HJ OEM PCBs behave similar

Kingston Teamgroup, V-Color, Corsair ~ behave similar (consumer tier)
Galax, Teamgroup ~ prosumer space behave different
ViperTW's theirs behaves slightly different
And G.Skill ones behave completely different.

---

EDIT:
Single Sided dimms may go by without any RTT_NOM
But likely behave better with some NOM ~ WR is the key factor for NOM & PARK behavior.

Thank you!
I will try to play with it, maybe I have to find the good key voltages again. But in that case I could adjust it here and there acc to the errors.

 

[Veii]

Thank you!
I will try to play with it, maybe I have to find the good key voltages again. But in that case I could adjust it here and there acc to the errors.

DIMM CA ODT keep how it is
CK, CS, CA factors in groups

lower value , stronger RTT_WR ~ messes with strength of both NOM & PARK
DQS is mostly (simplified) the connection point between CPU and MEM.
Soo up to ME and well global revision, it is either one tick under or one tick over PARK.
^ RTT being on DIMM, same applies to AMD users

I would focus to get weakest RTT_WR to run , and then see if somewhere it lacks current.
It is common to pump more VDIMM when you weaken RTTs or weaken supply strength.
But voltage itself means nothing. Not even heat~~

Beitrag automatisch zusammengeführt: 20.01.2024

lower value , stronger RTT_WR ~ messes with strength of both NOM & PARK

Like SA does for remain voltages. Very similar behavior, just direct (pyramid) ~ not indirect influence.
RTT_WR point messes with both.
It has the highest priority and values with it, vs without it behave different.

PARK & NOM go hand in hand with RRD and WTR behavior
Mostly with Bankgroup switching ~ so do also RTT go 🤝 with ODT values.
^ Aka mostly WR changes by capacity xor layout. Rest remains nearly identical unless layout changes

EDIT:
_NOM strength may need to increase by supplied higher voltage. So equally PARK may need to weaken. . .
But for DDR5 so far, 80ohm NOM is the most-optimal value.
This will very much change with CKD Dimms.

 

[tibcsi0407]

DIMM CA ODT keep how it is
CK, CS, CA factors in groups

lower value , stronger RTT_WR ~ messes with strength of both NOM & PARK
DQS is mostly (simplified) the connection point between CPU and MEM.
Soo up to ME and well global revision, it is either one tick under or one tick over PARK.
^ RTT being on DIMM, same applies to AMD users

I would focus to get weakest RTT_WR to run , and then see if somewhere it lacks current.
It is common to pump more VDIMM when you weaken RTTs or weaken supply strength.
But voltage itself means nothing. Not even heat~~

Beitrag automatisch zusammengeführt: 20.01.2024

Like SA does for remain voltages. Very similar behavior, just direct (pyramid) ~ not indirect influence.
RTT_WR point messes with both.
It has the highest priority and values with it, vs without it behave different.

PARK & NOM go hand in hand with RRD and WTR behavior
Mostly with Bankgroup switching ~ so do also RTT go 🤝 with ODT values.
^ Aka mostly WR changes by capacity xor layout. Rest remains nearly identical unless layout changes

EDIT:
_NOM strength may need to increase by supplied higher voltage. So equally PARK may need to weaken. . .
But for DDR5 so far, 80ohm NOM is the most-optimal value.
This will very much change with CKD Dimms.

Oh man, this will be complicated, but once if I get it, it will help a lot.
Chiller will also help a lot of I can fix the temperature of the coolant. With that I can remove another variable, the heat deltas.

 

[Veii]

Oh man, this will be complicated, but once if I get it, it will help a lot.

TM5 and trial and error 🤭

 

[tibcsi0407]

TM5 and trial and error 🤭

That will happen.

RX-DFE off.

Let's input your suggestions.

 

[Infi88]

You should be able to run tRDPDEN and tWRPDEN on 2 also. You cant tune the tWR value Intel IMC's dont have that register ignore the read outs and dial down tWRPRE instead , but 71 for 8600mhz is already pretty ok i think.

 

[tibcsi0407]

You should be able to run tRDPDEN and tWRPDEN on 2 also. You cant tune the tWR value Intel IMC's dont have that register ignore the read outs and dial down tWRPRE instead , but 71 for 8600mhz is already pretty ok i think.

Yes, should be okay, but pden 2 could mess the powerdown. Maybe it's not a good idea. It's a Buldzoid thing. 🙃