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I know it's hard to believe, but you can see it in most of his videos.
In the meantime I started to play with the RTT's. The combination you suggested got error code 55. Probably due to the low voltages.
I got a tip from @CarSalesman last year, so tried it. 34-120-80-40-40
I was able to boot it, but got error 0 iin 20. minutes. So I upped the Dqs to 48, now I got this:
Die Profis redet über extreme OC, ich hole jetzt andere Ergebnisse
Ich habe eine ziemlich gute 13700k, heute eingebaut.
Ich denke, es schaut nicht so schlegt aus. Ja ok, nicht so kraftig wie 14900k, aber gehts.
Delided, IHS drauf, LM ist zwischen Chip und IHS.
WLP ist zwischen Block und CPU.
13700k ist allcore 53p 42e 45r, und 2 Kerne boosted 54x.
Ich habe die ganze CPU Einstellungen so gelassen, wie Default ist. Nur habe ich die Best Case Scenario benutzt, die ein sehr gute UV ist.
Alle andere sind Default. Es gibt kein noch V/F, und solche Dinge.
Vcore getested kurze SFT, wenn es passt, dann alles passt. (Erste Bild)
Es war mit 5600 JEDEC, und danach 8000MHz eingegeben.
25 Rund TM5 ist sofort gegangen, und nacher VST/VT3 habe gestarted.
Wow, es hat mich gewundert, 50 Mins is gelaufen.
Nochmal, noch kein OC gibt, alles ist Default, nun 8000 plus paar Werte eingegeben.
Temperaturen sind auch schön
Ich mache weiter dann, nie aufgeben
Schöne Nacht u. WE an Alle!
Prost, zeb
Beitrag automatisch zusammengeführt:
Update:
Noch paar Werte eingegeben, und genau 50. Minutes Error. Immer VT3... grr, ich mag kein VT3 Test
For RD I need low (strong) value to even boot it. (48 is the highest which can boot) Is that means I already have high voltage on my dimms?
Should I lower the Voltage and increase the RD to 80?
Current state on 34-80-60-40-48. It's still running. RX-DFE on auto atm.
I was looking for the detailed comment from you about RTT's, but can't find it. Should be bookmarked somewhere I believe.
Current state on 34-80-60-40-48. It's still running. RX-DFE on auto atm.
I was looking for the detailed comment from you about RTT's, but can't find it. Should be bookmarked somewhere I believe.
DQS either one above or one bellow PARK
Dont match it.
Matching will require higher delta on pmic, to get some sort of usable distance between voltages.
NOM shenanigans indeed sounds like some different/odd behaving pcb.
I wonder.
Tuning RTTs on VDD/Q matched (in mem)
May be a good idea
But this will mess too much up.
Ya it looks fine.
You can play around if one NOM needs to be off or on
And you can play around between 40-48 PARK
If that changes how weak one NOM can reach.
Target remains 80-80. Those are not dual sided.
If you get RTTs figured out without DFE override, it will be top
RTTs need to be able to run and cover 1.44-1.6v
Actually they should be fine till 1.65 even
DQS either one above or one bellow PARK
Don't match it.
Matching will require higher delta on pmic, to get some sort of usable distance between voltages.
NOM shenanigans indeed sounds like some different/odd behaving pcb.
I wonder.
Tuning RTTs on VDD/Q matched (in mem)
May be a good idea
But this will mess up too much.
Ya it looks fine.
You can play around if one NOM needs to be off or on
And you can play around between 40-48 PARK
If that changes how weak one NOM can reach.
Target remains 80-80. Those are not dual sided.
Thank you. I believe the top settings could be the foundation now I will do more with RTT's again.
I start to believe that it could be doable. 🙃
Should I touch the ODT too?
No way around undervolt to lower UncoreVID.
Or limiting max ring multiplier.
Hitting PL4 means throttle.
How would it throttle.
At best package throttle, at worst voltage supply throttle
What happens if voltage is throttled too much ~ craaash 🤭
Mostly on cache
EDIT:
Unlimited ICCMAX makes no sense,
As you trade away cpu lifetime for "short time stability"
Fixing curve is the path~
To lower one part of supply, leave more margins till ICCMAX. Leave more margins for IMC.
Thank you. I believe the top settings could be the foundation now I will do more with RTT's again.
I start to believe that it could be doable. 🙃
Should I touch the ODT too?
You can just reuse them.
SA, VDD(2)_CPU, VDDQ_CPU
It either runs or doesnt.
But i would focus to keep SA lower.
VDDQ <-> MEM is an own topic.
Dont mind it for now.
We both know that things are cross connected
Low SA baseline is important. Else other voltages spike up and some lower.
Generally target since recent bioses is strong ODT.
Need to work with it.
Increasing SA is not the path to take. @mahaudi Karhu 20000%
Es braucht solange es braucht
No way around undervolt to lower UncoreVID.
Or limiting max ring multiplier.
Hitting PL4 means throttle.
How would it throttle.
At best package throttle, at worst voltage supply throttle
What happens if voltage is throttled too much ~ craaash 🤭
Mostly on cache
EDIT:
Unlimited ICCMAX makes no sense,
As you trade away cpu lifetime for "short time stability"
Fixing curve is the path~
To lower one part of supply, leave more margins till ICCMAX. Leave more margins for IMC.
Beitrag automatisch zusammengeführt:
You can just reuse them.
SA, VDD(2)_CPU, VDDQ_CPU
It either runs or doesnt.
But i would focus to keep SA lower.
VDDQ <-> MEM is an own topic.
Dont mind it for now.
We both know that things are cross connected
Low SA baseline is important. Else other voltages spike up and some lower.
Generally target since recent bioses is strong ODT.
Need to work with it.
Increasing SA is not the path to take. @mahaudi Karhu 20000%
Es braucht solange es braucht
Registered in this forum to try my luck finding tips.
Im currently on Encore with 7800Gskill Adies
I believe in "goal is always to overshoot in defensive side of things instead of always being at 1.0 ratio of cooling/clocks"
Im with barrow aluminium heatsinks with holes on top (great btw, 1.5mm pads) + noctua fan 2000rpm at ram
I did overclock to 8000c36 and 7800c34 but i didnt really gained anything in games and honestly i just want to gain MORE stability
I tried read about skew odts but honestly i am too dumb and dont have an osciloscope to really see it and hate doing guesses.
Im using xmp tweaked with few changes and zero voltage changes, maybe shamino settings is better than guessers in OCN and my guesses.
if anyone has an skew/odt recommendation to make what i have even more stable, thats my goal
any gain that isnt really pushing speeds
even lower vdd/vddq ram i accept any tip
even if no answers , the forum looks great, had alot of good reads.
im from brazil i use translate
edit: this is retrain stable 24h karhu 1h vst/n63/vt3 and performance is good, just wanna see if i can try anything else
i used to read recomendations from pahktunov/vei
but in ddr5 im just lost when it comes to ram powersaving(ppd and etc) and other uncommon settings, and encore have literally all, its depressing not know
Im using xmp tweaked with few changes and zero voltage changes, maybe shamino settings is better than guessers in OCN and my guesses.
if anyone has an skew/odt recommendation to make what i have even more stable, thats my goal
any gain that isnt really pushing speeds
even lower vdd/vddq ram i accept any tip
it just doesnt work that way
Being served on gold spoon - works for one person, doesnt work for other
And you dont learn by reading
But by trying out what you read.
No memory related voltages on auto
no cpu fixed clock, no cpu fixed voltage
I'm sorry if this comes over rude
But question read like , "explain me everything"
Ask question by question, and maybe it can be answered
Every question maybe has long or short explanation.
Its too much work and discouraging when asking "explain me everything".
ODT and RTT depend on mainboard
Depend on dimm
Depend on used voltage ~ which depend on CPU sample
Depend on PLL state.
Depend on hidden Bios settings, changing every 1-2 Bios releases.
Thing is i dont know what I am looking for. if there is something to look for
In past i would disable powerdown and selfrefresh, reading a bit aparently disabling it dont even disable it fully (and lowering the timings make pyprime faster so it does something)
and even if i set odts that work, how im supposed to know if my signal is less noisy/more correct
depth of knowledge = money and i dont have 100k$ for osciloscope xd
so maybe hints from ppl that know ppl with it. idk
being able to SEE is the first step to getting results, I honestly dont know how im supposed to know if X or Y is working just by stressing. it seens very guessable
edit: ram/latency is king of optimization so im just trying to make mine better while not pushing any stability boundaries
By pushing boundries and seeing what sticks
One can need lower voltage but still limit in max clock = too noisy
One can need much more voltage, but allow to scale higher than the dimm pcb was designed (example DDR4 , weak A0 PCB)
If you either push much, or start to learn on what many people call "g*rbage tier" or just bad bad cheap gear
You will understand when something "scales well".
This is the fun thing i had to learn
Lower is always faster somewhere.
On some application with some dataset size, big or small
You will always find some application where you can say "see it scales"
But thats always the case.
Lower is in specific type of read combinations or read, no-operation, read ~ always faster
some dont even leave one IC.
The question then becomes not about if the timing scales, but what was the tradeoff
What did you influence before set timing an what follows after set timings
Maybe its complicated and sounds like nonsense for somebody who only focuses on the result
But thats how i learned to stop just pushing pushing. And try to learn what happens and what do i pay with my changes
No timing goes alone
Absolutely zero.
Minimum has two links , often its 3 (before, target, effect after)
Money or lifetime , or connections
If you dig enough even if nobody wants to help you (take me as the best "worst example")
you still learn. Maybe not in 1month, maybe its difficult for 5 months
But after 6-8 years being silly and fooling around ~ you sloowly start to understand.
I'm still novice, but even if you hold bad of me (example)
I learned a bit. Day by day more. Soo if low-iq me can do it ~ everybody can.
just work harder 🤭 and don't forget your goals
This might sound naive from me
But it is really not the case
Latency matters only to be faster than inter-thread/inner-cpu latency
Soo priority to leave cache and leak to mem, vs other cores ~ is higher.
If memory access is fast enough, decision to pick that path is rather whats going to happen ~ vs make roundtrip and stay on cpu side.
Latency only is a variable vs how the cpu behaves.
Some SKUs scale more, some less, some who use huge L3 cache or fast V-Cache
~ its hard on them to tell to leak to memory, when memory maybe differs between 15-20GB/s, but internally it runs at 500GB/s with same latency . . . for example
^ like why should CPU even bother to leak to mem, instead of wait a bit and process it much faster or split around other free cores~
Many many IF's
Try to get familiar with SiSoftware Sandra.
Don't rely too much on those little memory filling random-type of benchmarks.
They will show one scenario, but memory can be optimized, for all sorts of different workloads.
Its not a simple or straightforward thing.
Because how would you define "faster" or "slower"
if you only test in one made up coded scenario.
How can you tell its actually "faster".
How can you tell its not just using one timing more, because the target/workload is just such little one.
Try to look at the bigger picture~
No timing goes alone
Lower Clock = lower visual timings.
but timings are just placeholders. The value is just visual without any meaning
It gets a meaning when you compare it to what type of clock ~ how much, it actually is
And still then - first target is stability high clock.
Timings are just gifts. Extras. They have low priority.
How things interact with each other, is more important.
And of-course absolute stability.
im really demotivated to deep dive cause it will be guesses..
an pc is faster cause he can do instructions faster
not cause it has been overclocked higher "grain of salt"xd
im more interested in architecture and his awful relationship with scheduler/os
but i came to the right place, the insight fullfilled me on what to do a bit
most overclocks i see put more stress on the arch and is just average fps streetching with barely any gains on lows where it actually improve ur experience
i cannot get access to any good pdf to read (last time i tried some intel pdf i got the text "it's a confidential slidedeck so I'm not too comfortable putting it "out there" without the proper approvals") but still managed to find a bios setting that learn that it was Power Control Unit/throttling that i was able to disable and get 80w more of my cpu at same load, was fun)
and too dumb to get an conclusion from jedec
just one objective question, do you think i am wrong of disabling powerdown and set timings to minimum register
it showed no signs of unstability, improved some benchs(will try what u recommended), and i do that cause of 10y old pdfs that i read about them,
Now powerdown is part of self-refresh
and self refresh is part of FGR. Clock-Halting is also a fun new thing.
FGR especially is mostly used on LPDDR4 (onwards) and you will find information on GDDR5++
Everything LPDDR4 can do, DDR5 can do.
Just DDR5 changed from where many things were under MSR ~ they are now API calls.
DDR5 became a standalone ecosystem similar to your GPU.
Setting timings to lowest point, will harm some timings before and some timings after.
// Because many things - multiple timings happen at the same time !
JEDEC paper i still "don't understand" fully.
But they (memory committee, jedec is there for all sorts behavior) - pads/paste/nand-flash/thermal behavior, pcb layering and targets . . . many things
Are the first source you can use as "this is how it will be , if nothing was changed mid or past design" . Especially when DDR5 is still in its young age.
Like "this is the target and this is how it has to be. Change it up a bit , but still this is how it behaves and can behave". The bare minimum required targets for IC design.
On that part you can be sure.
Its like other global comitee's that set the standard and thats how things are and will be.
Its your book to see if you misunderstood something and check if you broke some rule.
Memory will do its best to correct and jedec papers do not define all sort of use-cases
^ couple interesting ones ~ last is complex and becomes interesting on AMDs side.
For example , and similar from https://ieeexplore.ieee.org/
Be it for GDDR or LPDDR or own designed FPGA circuits.
I can guarantee there is always some snippets of information that you can use
If you search how to get those papers, it will help.
I can not be the person that helps in going around university restrictions.
Even if as researcher person think knowledge should be free for everyone.
Nvidia has early on employed some tallented Memory Researchers
There might be some information out on this for LPDDR4 and GDDR.
There are parallels. Just the link layout and location layout differs a bit.
Else they are still very similar to consumer ICs.
Its unfortunate that NDA mentality is a thing.
Rivalism and secret-keeping is strong in this industry Unfortunately that halts global progress, but money i guess~
* Soo you still need to work a bit for your goal.
Just don't forget your goals ~ and if you learn or be successful, give back and help more people
If you don't, you do no change to this "hard to find information" issue. So other people will equally struggle like you did.
EDIT2:
Here are some writeups from one blogger on CSDN [CN]
文章浏览阅读4k次,点赞4次,收藏58次。2020年2月6日,美光科技宣布交付全球首款量产的低功耗DDR5 DRAM 芯片,随后,三星S20系列和小米10系列手机先后发布,全新的LPDDR5内存成为两家的共同卖点之一,这也预示着DDR5的时代即将到来。今天我们就来聊一聊DDR5的发展过程,设计难题以及如何通过仿真来应对DDR5设计挑战。本文主要目录:01.DDR技术的发展历程02.DDR5的出现,带来了哪些设计挑战?03.如何通过仿真及建模中的创新克服DDR5技术挑战04.DDR5仿真解决方案05.DDR5仿真实例..._ddr5仿真
If you want to figure things out ~ you'll figure things out 🤭
But i've given enough, now its on you to dig and slowly with multiple readings try to understand
And not only read and try to understand
But play around.
With imagining to guess, nothing works. With trial and error you will understand
Many people hand out information, but spoonfeeding is not ok.
"gifted" vendor-documents and knowledge are earned, not handed out just like this.