Du verwendest einen veralteten Browser. Es ist möglich, dass diese oder andere Websites nicht korrekt angezeigt werden. Du solltest ein Upgrade durchführen oder einen alternativen Browser verwenden.
Yes, you were right. I am starting from scratch, memory all auto. So far LLC 4, AC 0.3 / DC 1.02 and it is fully stable. This, with my old 8000 memOC, was unstable. However I am not yet playing with the V/F curve and SVID is still AUTO. Want to solve LLC AC DC first. Sorry for not posting any result yet, it will come.
So sorry I doubted the reason for the instability as you said. I am not going to do it again!
Wenn Du diese Anzeige nicht sehen willst, registriere Dich und/oder logge Dich ein.
Yes, you were right. I am starting from scratch, memory all auto. So far LLC 4, AC 0.3 / DC 1.02 and it is fully stable. This, with my old 8000 memOC, was unstable. However I am not yet playing with the V/F curve and SVID is still AUTO. Want to solve LLC AC DC first. Sorry for not posting any result yet, it will come.
So sorry I doubted the reason for the instability as you said. I am not going to do it again!
Hey, i make mistakes too.
If memOC is/was ok, then its ring messing with it.
I believe the curve is fine.
Tho i am human, i can make mistakes 🤭
0.6 to 1ohm IA_AC is a huge range. Probably near 80-100W difference.
Just logically, if IA supply is a chunk
Ring takes from it, e-cores take from it, cores take from it, imc takes from it
It is kind of logical that IMC may lack voltage. Or ring clocks higher, and steals too much.
VID is dynamic.
I need to actually go and check skatterbencher's roundup and explanation on this topic ~ haven't read anything by him on it.
Researching neutrally. Probably miss some little nouance.
But PL4 aka ICCMAX factors in allowed voltages for everything,, outside that we just aim to never have 1.4v VID requests.
Someday i want to know why this "MC ceiling" exists on some CPUs. But honestly, its time to save up and buy a 14th gen
Unsure yet, too expensive~ @Vhypur
Current OCN ~ CKD on Dimms Topic
Micron initially wanted to use them , to what i remember
And if i find back the articles and PDF, i'll ping you
But they don't really need "compatibility"
Rep wasnt wrong about "drop in replacement for AM5 and LGA1700".
Targeting 6400 JEDEC out of the box.
Boardpartners may need to push a bios update out for it
But that's my smallest worry, because first they know their work, and 2nd its been tested already.
Old bioses should have support. Very likely ~ 85% sure.
Else yes RDIMM may be able to use it
They sit right under the ICs , similar to PCI Redrivers but 1/3rd the size.
Given most communication is done via i²c ~ PCB changes don't really need CPU approval. RTTs sit on-dimm too.
DDR5 was designed as a standalone ecosystem. Unlike DDR4
You synchronize with DDR5, you don't really actively control it. Just communicate.
Kannst du mir bitte nochmal 50mV von VDDQ_CPU entfernen und VDDQ Training auf aus
Oder anstelle dem Training auf aus (gehört sich eig so), ein PSU off ~ 1min, coldboot anschmeißen ?
Just logically, if IA supply is a chunk
Ring takes from it, e-cores take from it, cores take from it, imc takes from it
It is kind of logical that IMC may lack voltage. Or ring clocks higher, and steals too much.
@Abtrünnig
If IMC lacks voltage, lower target SA.
Sounds counterproductive, but IMC actually knows how much to take
Soo strengthen VDD MC Link too, if you think you need more
And then just get VDDQ_CPU to VDDQ_MEM with around 120mV delta. 75-200mV .
Range will depend on many factors for Vref. One of them is if MEM side uses delta or not.
Mem delta of 60mV is healthy. Max there is 300mV not 200mV ~ correction for X who reads it.
Mem delta of 100mV always works ~ but always, means user can be a variable and bad RTTs will prevent this "always" factor.
60mV is nothing and should work for everyone
Higher delta on mem side = higher delta on cpu to mem link.
Kannst du mir bitte nochmal 50mV von VDDQ_CPU entfernen und VDDQ Training auf aus
Oder anstelle dem Training auf aus (gehört sich eig so), ein PSU off ~ 1min, coldboot anschmeißen ?
🙏📿
Müsste ok sein.
Es gibt margins
Im schlimmsten Fall, SA runter. 1.22 klingt ganz ok, anstelle 1.25. *
Das ändert das MC und TX verhalten.
* 1.18 klingt sogar noch besser, aber schritt für schritt~
1.4 VDD(2)_CPU ist halt auch eher für +8200MT/s gedacht , haha
Du hast noch Spielraum.
Kannst du mir bitte nochmal 50mV von VDDQ_CPU entfernen und VDDQ Training auf aus
Oder anstelle dem Training auf aus (gehört sich eig so), ein PSU off ~ 1min, coldboot anschmeißen ?
@Veii
wenn das so durchläuft, kann ich die Spannungen dann auch niedrigere raten übertragen ?
also gleiche Spannungen nur zum Beispiel 7600 statt 7800 ?
@Veii
wenn das so durchläuft, kann ich die Spannungen dann auch niedrigere raten übertragen ?
also gleiche Spannungen nur zum Beispiel 7600 statt 7800 ?
VDDQ's gehen zusammen
VDD(2)_CPU skalliert pro clock, aber du rennst mehr als genug davon
SA ist der Hauptbaustein für die CPU Spannungen
VDD_MEM skaliert mit den Timings.
VDDQ[_MEM] ist der Connection-Point zwischen beide Leitungen.
Du musst dir genauer anschauen wie tief SA gehen kann.
Es hat mehr einfluss auf die CPU ODT, als nur eine einzelne Spannung zu sein.
Unter 1.2v SA, ändert sich vieles
Über 1.3v SA ebenso
Ich denke über 1.25 SA gibt es einen Zwischenschritt.
Es kommt auf deine CPU an was sie mag.
Soweit ist niedrige Spannung immer besser.
Versuche VDD(2)_CPU niemals über VDD_MEM zu rennen.
Sowie niemals unter SA.
Sobald man beide VDDQ's einmal hat, sollte man sie nicht mehr anfassen.
Es ist nerviger aber gut ohne VDDQ Training zu starten, damit das Board keine versteckte Korrektur vornehmen kann.
Sprich es liegt nur an dir die Korrekten Werte auszuloten.
VDDQ's gehen zusammen
VDD(2)_CPU skalliert pro clock, aber du rennst mehr als genug davon
SA ist der Hauptbaustein für die CPU Spannungen
VDD_MEM skaliert mit den Timings.
VDDQ[_MEM] ist der Connection-Point zwischen beide Leitungen.
Du musst dir genauer anschauen wie tief SA gehen kann.
Es hat mehr einfluss auf die CPU ODT, als nur eine einzelne Spannung zu sein.
Unter 1.2v SA, ändert sich vieles
Über 1.3v SA ebenso
Ich denke über 1.25 SA gibt es einen Zwischenschritt.
Es kommt auf deine CPU an was sie mag.
Soweit ist niedrige Spannung immer besser.
Versuche VDD(2)_CPU niemals über VDD_MEM zu rennen.
Sowie niemals unter SA.
Sobald man beide VDDQ's einmal hat, sollte man sie nicht mehr anfassen.
Es ist nerviger aber gut ohne VDDQ Training zu starten, damit das Board keine versteckte Korrektur vornehmen kann.
Sprich es liegt nur an dir die Korrekten Werte auszuloten.
@Vhypur
Current OCN ~ CKD on Dimms Topic
Micron initially wanted to use them, to what I remember
And if I find back the articles and PDF, I'll ping you
But they don't really need "compatibility"
Rep wasn't wrong about "drop in replacement for AM5 and LGA1700".
Targeting 6400 JEDEC out of the box.
Board partners may need to push a bios update out for it
But that's my smallest worry, because first they know their work, and 2nd its been tested already.
Old bioses should have support. Very likely ~ 85% sure.
Else yes RDIMM may be able to use it
They sit right under the ICs, similar to PCI Redrivers but 1/3rd the size.
Given most communication is done via i²c ~ PCB changes don't really need CPU approval. RTTs sit on-dimm too.
DDR5 was designed as a standalone ecosystem. Unlike DDR4
You synchronize with DDR5, you don't really actively control it. Just communicate.
Ah ok tyty i def need to readup more into this stuff, alot of info in general on anything ddr5 related is pretty rough to find including the correct correct values/formulas or what does/doesn't work with certain stuff, i have some questions i don't wanna bug ya too much though but if you don't mind i'll think on it a little and just toss them all in 1 post, mostly ddr5 related but a couple cpu things
Das teste ich gleich morgen Abend mal und gebe dir Bescheid. Und wenn wir es ohne GDM zum laufen kriegen, gebe ich dir einen aus :) @z3r0.c0m , kannst du bitte hier öffentlich Updates darlassen ? Ich bin ungerne Techsupport und weitaus weniger gern helfe ich Privat. Keine techsupport PMs...
www.hardwareluxx.de
Der Post, bzw der Rücklinkende erklärt es gut.
Q heißt zwar Daten
S wäre strobe ~ "strom" , der Differenzstrom (differencial-current)
VDD ist die Spannung
DQ ist die Datenverbindung
DQS ist die Stromverbindung.
VDDQ baut den Vref. EDIT:
Halb.
Vref für DQ & CA wird durch ein Gain Factor und % von VDDQ bestimmt
Dies geht durch CTLE (optional), durch DFE am TX (eventuell) und landet auf DFE am RX ~ bevor durch write leveling , optimal alle korrekt "alignen"
Da DQs durch die Distanz immer etwas verzögert sind. Besonders bei zwei subchannels., pro Dimm. DQS und Clock syncronizieren sich schon bei dem Training.
DQS & Clock synchronisieren sich. Alle DQs synchronisieren sich.
@Veii
Could you please suggest me a good tWRRD_sg dg pair?
Is this too low?
Afaik ASRTC math is not correct for tWTR values.
I can't boot with 62/48 but didn't try 62/50.
Acc. to the rules for getting TWTR L / S = tWRRD-tCWL-2
Am I right?
I want to first set the timings to perfect before even playing with the voltages.
Don't touch that, just fix tWTR_
Board is intelligent.
Bothersome to make 4 changes and offset of CAS/CWL change ~ every clock.
tWRRD_X = tCCD_L
This table is fine
"recommended" but lower is faster.
No real limitation. Users lower tWTR_L by default to run tight terts or tight WR
Common seen behavior. Its wrong.
Math has no need to be tWTR_L either.
4 ways exist. tWTR_A is a thing. Past first write is instant, 2nd WR is delayed by BC8.
Real duration depends if command ends with autoprecharge or not.
tWR wont just start if conflict is happening.
Don't touch that, just fix tWTR_
Board is intelligent.
Bothersome to make 4 changes and offset of CAS/CWL change ~ every clock.
WRRD = CCDDL
This table is fine Anhang anzeigen 960472
"recommended" but lower is faster.
No real limitation. Users lower tWTR_L by default to run tight terts or tight WR
Common seen behavior. It's wrong.
Math has no need to be tWTR_L either.
4 ways exist. tWTR_A is a thing. Past first write is instant, 2nd WR is delayed by BC8.
Real duration depends if command ends with autoprecharge or not.
tWR wont just start if conflict is happening.
For both "it depends"
CCDL lower = perf win, in exchange of instability.
AP end commands have fun behavior.
WTRA & WR topic is very fun. 4 answers are correct.
Or jump to 9600 for Gear4. Easy Game. (on your & zebra's CPU)
Or take a break.
Beitrag automatisch zusammengeführt:
Sugi plays in 9000 Club.
Its fun.
Also RCD 49 is quite tight . Maybe too much for 8600, if i compare other results.
If you want to spare time with 8600, i would recommend to invest time working with DFE and CTLE.
Then 8800 might become in reach.
Because 8400+ with bad DFE is already ... a fairy tale
It must be at least somewhat ok, to see you can run it higher
But my trust is limited that Board is perfect ~ yet.
Better Databuffer on DIMM soon will make it better
But, eh i dont know. Feeling says its not going around main speed problem past 8400.
Which is Noise and DFE topic.
Break is not an option. 🙃 (Little devil in my head always whispers to push higher)
Then I will jump to 8600, set my old settings. That was only possible with HT off so far.
If signal looks anywhere near remotely that good on 8400.
Then there is much headroom left.
I do think we are slightly better than left, but nowhere near close to right.
Just my feelings on current reality.
We'll start to have to use other tools, because ASUS HigherUp's do not like open bioses.
But thats the path i see.
Users lack access to FFE, CTLE and DFE.
But especially CTLE and DFE are soo crucial to reaching higher tier clock.
How can one have fun with Gear4 , when core basic DDR5 design functionality is not given.
Just "on / off" ~ but thats not enough.
Writeleveling last time i checked was bugged. But i was a bit amateur, soo maybe its on me.
I dont know~
Feels it needs more manual labor before users can "just run" 8400.
Speaking of, @CarSalesman ~ under NDA ??
Any hints on debug menu ?
Whats the purpose of messing up boards semi-saved training , when you run old voltages on old profile ?
Scaling up doesnt work ?
Start fresh and just scale up
Whats the purpose of messing up boards semi-saved training , when you run old voltages on old profile ?
Scaling up doesnt work ?
Start fresh and just scale up
No, it boots, but stability is an other thing. I can even boot and run some bench on 8800.
I passed TM5 10 cycles several times, 10 minutes Y was the max I tried, but with HT is a different story.
I didn't load that profile, set everything from scratch. We will see how it performs.
The TM5 was a strange one, I was able to pass it with 1.47V VDD and 1.56V VDD nothing worked between.
Maybe it's the skew training.
This will be the base of the 8600 profile. Maybe Trc and Trp should be changed later to 50 or 51 we will see.
I left WTR's and tWRRD's on auto and let Tweak mode 2 to set it. It's quite tight actually.
Dqvref set by your suggestion to 182 / 100.
Thanks for the latest ASRTC.
No, it boots, but stability is an other thing. I can even boot and run some bench on 8800.
I passed TM5 10 cycles several times, 10 minutes Y was the max I tried, but with HT is a different story.
I didn't load that profile, set everything from scratch. We will see how it performs.
The TM5 was a strange one, I was able to pass it with 1.47V VDD and 1.56V VDD nothing worked between.
Maybe it's the skew training.
www.hardwareluxx.de
