Am WE werde ich endlich mal meine Virgin R-Batch und den KS auspacken .... touched for the very first time.
Auch dein Speicherkit?
[Sammelthread] Intel DDR5 RAM OC Thread
- Ersteller even.de
- Erstellt am
Auch dein Speicherkit?
7600 posten, aber Win10 startet dann direkt mir "Repair" und schmiert ab. 7400 sind durch, 7500 booten immerhin noch.. versuch ich noch y-cruncher.
Aber wie du meintest, die gehen leichter hoch als 32GB A-Die. Liegt es an den M-Die? Ginge das auch mit 32GB M-Die?
Aber wie du meintest, die gehen leichter hoch als 32GB A-Die. Liegt es an den M-Die? Ginge das auch mit 32GB M-Die?
H16M ist nicht mehr relevant. Die 24Gbit ICs sind irgendwie leichter für den IMC, aber fürs Benchen zum größten Teil uninteressant.
IronAge
Legende
H16M finde ich wegen der Latenzen eigentlich ganz schick, auf dem DARK laufen die doch sehr gut, auch mit CR1.
Am WE werde ich endlich mal meine Virgin R-Batch und den KS auspacken .... touched for the very first time.
An welchem WE genau? Da werde ich mal reinschauen.
IronAge
Legende
Wenn mir danach ist lass ich es dich wissen. Der Kühlungs-Kram liegt eh noch in Umzugskartons und mir fehlt mindestens ein 360er Radi.
Der Kühlungs-Kram liegt eh noch in Umzugskartons und mir fehlt mindestens ein 360er Radi.
IronAge
Legende
Ne, aber das Montagematerial für die AC AIO schon, und meine Glotzbebbl wollen auch schon nicht mehr, muss wieder in die Uniklinik. 🤮
zebra_hun
Profi
OK, es ist nur fuer Spass. Repaired das Profil, jetzt gibts kein error unter VST/VT3.
Die zwei Spannungen fixiert, aber die Rest auto geblieben sind.
Loesung glaube ich meine fanatik low Vcore erhoeht. Anstatt 1.057V zu 1.066V.
Ich bin aber nicht sicher, ob das Profil gesund fuer Alltags. Viel zu viel Spannung kostet.
ZB.:
8000C36 1.41V (alte CPU, mit neuem 1.425V)
8000C34 1.515V
Ich habe garnichts gebench mit dem Profil, aber es denke ich, lohn sich nicht. Schau mal moi
werde ich es machen spaeter.Wenn Jemand reingucken moechte, hier ist komplette
[2024/04/14 11:41:29]
Ai Overclock Tuner [Manual]
BCLK Frequency [100.0000]
PCIE Frequency [100.0000]
Intel(R) Adaptive Boost Technology [Auto]
ASUS MultiCore Enhancement [Enabled – Remove All limits (90°C)]
SVID Behavior [Trained]
BCLK Frequency : DRAM Frequency Ratio [100:100]
Memory Controller : DRAM Frequency Ratio [1:2]
DRAM Frequency [DDR5-8000MHz]
Performance Core Ratio [By Core Usage]
1-Core Ratio Limit [57]
2-Core Ratio Limit [57]
3-Core Ratio Limit [56]
4-Core Ratio Limit [56]
5-Core Ratio Limit [55]
6-Core Ratio Limit [55]
7-Core Ratio Limit [54]
8-Core Ratio Limit [54]
Performance Core0 Specific Ratio Limit [Auto]
Performance Core0 specific Voltage [Auto]
Performance Core1 Specific Ratio Limit [Auto]
Performance Core1 specific Voltage [Auto]
*Performance Core2 Specific Ratio Limit [Auto]
Performance Core2 specific Voltage [Auto]
*Performance Core3 Specific Ratio Limit [Auto]
Performance Core3 specific Voltage [Auto]
Performance Core4 Specific Ratio Limit [Auto]
Performance Core4 specific Voltage [Auto]
Performance Core5 Specific Ratio Limit [Auto]
Performance Core5 specific Voltage [Auto]
Performance Core6 Specific Ratio Limit [Auto]
Performance Core6 specific Voltage [Auto]
Performance Core7 Specific Ratio Limit [Auto]
Performance Core7 specific Voltage [Auto]
Efficient Core Ratio [By Core Usage]
Efficient Turbo Ratio Limit 1 [43]
Efficient Turbo Ratio Cores 1 [Auto]
Efficient Core Group0 Specific Ratio Limit [Auto]
Efficient Core Group0 specific Voltage [Auto]
Efficient Core Group1 Specific Ratio Limit [Auto]
Efficient Core Group1 specific Voltage [Auto]
Efficient Core Group2 Specific Ratio Limit [Auto]
Efficient Core Group2 specific Voltage [Auto]
Efficient Core Group3 Specific Ratio Limit [Auto]
Efficient Core Group3 specific Voltage [Auto]
AVX2 [Auto]
AVX2 Ratio Offset to per-core Ratio Limit [Auto]
AVX2 Voltage Guardband Scale Factor [Auto]
Maximus Tweak [Mode 2]
DRAM CAS# Latency [34]
DRAM RAS# to CAS# Delay Read [45]
DRAM RAS# to CAS# Delay Write [25]
DRAM RAS# PRE Time [45]
DRAM RAS# ACT Time [61]
DRAM Command Rate [2N]
DRAM RAS# to RAS# Delay L [8]
DRAM RAS# to RAS# Delay S [8]
DRAM REF Cycle Time 2 [480]
DRAM REF Cycle Time Same Bank [448]
DRAM Refresh Interval [262143]
DRAM WRITE Recovery Time [24]
DRAM READ to PRE Time [12]
DRAM FOUR ACT WIN Time [32]
DRAM WRITE to READ Delay L [16]
DRAM WRITE to READ Delay S [4]
DRAM CKE Minimum Pulse Width [20]
DRAM Write Latency [32]
Ctl0 dqvrefup [170]
Ctl0 dqvrefdn [88]
Ctl0 dqodtvrefup [Auto]
Ctl0 dqodtvrefdn [Auto]
Ctl1 cmdvrefup [Auto]
Ctl1 ctlvrefup [Auto]
Ctl1 clkvrefup [Auto]
Ctl1 ckecsvrefup [Auto]
Ctl2 cmdvrefdn [Auto]
Ctl2 ctlvrefdn [Auto]
Ctl2 clkvrefdn [Auto]
Read Equalization RxEq Start Sign [-]
Read Equalization RxEq Start [Auto]
Read Equalization RxEq Stop Sign [-]
Read Equalization RxEq Stop [Auto]
ODT_READ_DURATION [Auto]
ODT_READ_DELAY [Auto]
ODT_WRITE_DURATION [Auto]
ODT_WRITE_DELAY [Auto]
DQ RTT WR [40 DRAM Clock]
DQ RTT NOM RD [40 DRAM Clock]
DQ RTT NOM WR [34 DRAM Clock]
DQ RTT PARK [34 DRAM Clock]
DQ RTT PARK DQS [34 DRAM Clock]
GroupA CA ODT [240 DRAM Clock]
GroupA CS ODT [0 DRAM Clock]
GroupA CK ODT [0 DRAM Clock]
GroupB CA ODT [60 DRAM Clock]
GroupB CS ODT [40 DRAM Clock]
GroupB CK ODT [40 DRAM Clock]
Pull-up Output Driver Impedance [48 DRAM Clock]
Pull-Down Output Driver Impedance [40 DRAM Clock]
DQ RTT WR [40 DRAM Clock]
DQ RTT NOM RD [40 DRAM Clock]
DQ RTT NOM WR [34 DRAM Clock]
DQ RTT PARK [34 DRAM Clock]
DQ RTT PARK DQS [34 DRAM Clock]
GroupA CA ODT [240 DRAM Clock]
GroupA CS ODT [0 DRAM Clock]
GroupA CK ODT [0 DRAM Clock]
GroupB CA ODT [60 DRAM Clock]
GroupB CS ODT [40 DRAM Clock]
GroupB CK ODT [40 DRAM Clock]
Pull-up Output Driver Impedance [40 DRAM Clock]
Pull-Down Output Driver Impedance [48 DRAM Clock]
Round Trip Latency Init Value MC0 CHA [Auto]
Round Trip Latency Max Value MC0 CHA [Auto]
Round Trip Latency Offset Value Mode Sign MC0 CHA [-]
Round Trip Latency Offset Value MC0 CHA [Auto]
Round Trip Latency Init Value MC0 CHB [Auto]
Round Trip Latency Max Value MC0 CHB [Auto]
Round Trip Latency Offset Value Mode Sign MC0 CHB [-]
Round Trip Latency Offset Value MC0 CHB [Auto]
Round Trip Latency Init Value MC1 CHA [Auto]
Round Trip Latency Max Value MC1 CHA [Auto]
Round Trip Latency Offset Value Mode Sign MC1 CHA [-]
Round Trip Latency Offset Value MC1 CHA [Auto]
Round Trip Latency Init Value MC1 CHB [Auto]
Round Trip Latency Max Value MC1 CHB [Auto]
Round Trip Latency Offset Value Mode Sign MC1 CHB [-]
Round Trip Latency Offset Value MC1 CHB [Auto]
Round Trip Latency MC0 CHA R0 [Auto]
Round Trip Latency MC0 CHA R1 [Auto]
Round Trip Latency MC0 CHA R2 [0]
Round Trip Latency MC0 CHA R3 [0]
Round Trip Latency MC0 CHA R4 [0]
Round Trip Latency MC0 CHA R5 [0]
Round Trip Latency MC0 CHA R6 [0]
Round Trip Latency MC0 CHA R7 [0]
Round Trip Latency MC0 CHB R0 [Auto]
Round Trip Latency MC0 CHB R1 [Auto]
Round Trip Latency MC0 CHB R2 [0]
Round Trip Latency MC0 CHB R3 [0]
Round Trip Latency MC0 CHB R4 [0]
Round Trip Latency MC0 CHB R5 [0]
Round Trip Latency MC0 CHB R6 [0]
Round Trip Latency MC0 CHB R7 [0]
Round Trip Latency MC1 CHA R0 [Auto]
Round Trip Latency MC1 CHA R1 [Auto]
Round Trip Latency MC1 CHA R2 [0]
Round Trip Latency MC1 CHA R3 [0]
Round Trip Latency MC1 CHA R4 [0]
Round Trip Latency MC1 CHA R5 [0]
Round Trip Latency MC1 CHA R6 [0]
Round Trip Latency MC1 CHA R7 [0]
Round Trip Latency MC1 CHB R0 [Auto]
Round Trip Latency MC1 CHB R1 [Auto]
Round Trip Latency MC1 CHB R2 [0]
Round Trip Latency MC1 CHB R3 [0]
Round Trip Latency MC1 CHB R4 [0]
Round Trip Latency MC1 CHB R5 [0]
Round Trip Latency MC1 CHB R6 [0]
Round Trip Latency MC1 CHB R7 [0]
Early Command Training [Auto]
SenseAmp Offset Training [Auto]
Early ReadMPR Timing Centering 2D [Auto]
Read MPR Training [Auto]
Receive Enable Training [Auto]
Jedec Write Leveling [Auto]
Early Write Time Centering 2D [Auto]
Early Read Time Centering 2D [Auto]
Write Timing Centering 1D [Auto]
Write Voltage Centering 1D [Auto]
Read Timing Centering 1D [Auto]
Read Timing Centering with JR [Auto]
Dimm ODT Training* [Disabled]
Max RTT_WR [ODT Off]
DIMM RON Training* [Disabled]
Write Drive Strength/Equalization 2D* [Auto]
Write Slew Rate Training* [Auto]
Read ODT Training* [Disabled]
Comp Optimization Training [Auto]
Read Equalization Training* [Auto]
Read Amplifier Training* [Auto]
Write Timing Centering 2D [Auto]
Read Timing Centering 2D [Auto]
Command Voltage Centering [Auto]
Early Command Voltage Centering [Auto]
Write Voltage Centering 2D [Auto]
Read Voltage Centering 2D [Auto]
Late Command Training [Auto]
Round Trip Latency [Auto]
Turn Around Timing Training [Auto]
CMD CTL CLK Slew Rate [Auto]
CMD/CTL DS & E 2D [Auto]
Read Voltage Centering 1D [Auto]
TxDqTCO Comp Training* [Auto]
ClkTCO Comp Training* [Auto]
TxDqsTCO Comp Training* [Auto]
VccDLL Bypass Training [Auto]
CMD/CTL Drive Strength Up/Dn 2D [Auto]
DIMM CA ODT Training [Auto]
PanicVttDnLp Training* [Auto]
Read Vref Decap Training* [Auto]
Vddq Training [Disabled]
Duty Cycle Correction Training [Auto]
Periodic DCC [Auto]
Rank Margin Tool Per Bit [Auto]
DIMM DFE Training [Auto]
EARLY DIMM DFE Training [Auto]
Tx Dqs Dcc Training [Auto]
DRAM DCA Training [Auto]
Write Driver Strength Training [Auto]
Rank Margin Tool [Auto]
Memory Test [Auto]
DIMM SPD Alias Test [Auto]
Receive Enable Centering 1D [Auto]
Retrain Margin Check [Auto]
Write Drive Strength Up/Dn independently [Auto]
LPDDR DqDqs Re-Training [Auto]
Margin Check Limit [Disabled]
tRDRD_sg_Training [Auto]
tRDRD_sg_Runtime [16]
tRDRD_dg_Training [Auto]
tRDRD_dg_Runtime [8]
tRDWR_sg [20]
tRDWR_dg [20]
tWRWR_sg [16]
tWRWR_dg [8]
tWRRD_sg [Auto]
tWRRD_dg [Auto]
tRDRD_dr [1]
tRDRD_dd [0]
tRDWR_dr [1]
tRDWR_dd [0]
tWRWR_dr [1]
tWRWR_dd [0]
tWRRD_dr [1]
tWRRD_dd [0]
tRPRE [Auto]
tWPRE [Auto]
tWPOST [Auto]
tWRPRE [Auto]
tPRPDEN [Auto]
tRDPDEN [Auto]
tWRPDEN [Auto]
tCPDED [Auto]
tREFIX9 [Auto]
Ref Interval [Auto]
tXPDLL [Auto]
tXP [Auto]
tPPD [2]
tCCD_L_tDLLK [Auto]
tZQCAL [Auto]
tZQCS [Auto]
OREF_RI [Auto]
Refresh Watermarks [High]
Refresh Hp Wm [Auto]
Refresh Panic Wm [Auto]
Refresh Abr Release [Auto]
tXSDLL [Auto]
tZQOPER [Auto]
tMOD [Auto]
CounttREFIWhileRefEn [Auto]
HPRefOnMRS [Auto]
SRX Ref Debits [Auto]
RAISE BLK WAIT [Auto]
Ref Stagger En [Auto]
Ref Stagger Mode [Auto]
Disable Stolen Refresh [Auto]
En Ref Type Display [Auto]
Trefipulse Stagger Disable [Auto]
tRPab ext [Auto]
derating ext [Auto]
Allow 2cyc B2B LPDDR [Auto]
tCSH [Auto]
tCSL [Auto]
powerdown Enable [Auto]
idle length [Auto]
raise cke after exit latency [Auto]
powerdown latency [Auto]
powerdown length [Auto]
selfrefresh latency [Auto]
selfrefresh length [Auto]
ckevalid length [Auto]
ckevalid enable [Auto]
idle enable [Auto]
selfrefresh enable [Auto]
Address mirror [Auto]
no gear4 param divide [Auto]
x8 device [Auto]
no gear2 param divide [Auto]
ddr 1dpc split ranks on subch [Auto]
write0 enable [Auto]
MultiCycCmd [Auto]
WCKDiffLowInIdle [Auto]
PBR Disable [Auto]
PBR OOO Dis [Auto]
PBR Disable on hot [Auto]
PBR Exit on Idle Cnt [Auto]
tXSR [Auto]
Dec tCWL [Auto]
Add tCWL [Auto]
Add 1Qclk delay [Auto]
MRC Fast Boot [Disabled]
MCH Full Check [Auto]
Mem Over Clock Fail Count [3]
Training Profile [ASUS User Profile]
RxDfe [Enabled]
Mrc Training Loop Count [3]
DRAM CLK Period [Auto]
Dll_bwsel [Auto]
Controller 0, Channel 0 Control [Enabled]
Controller 0, Channel 1 Control [Enabled]
Controller 1, Channel 0 Control [Enabled]
Controller 1, Channel 1 Control [Enabled]
MC_Vref0 [Auto]
MC_Vref1 [Auto]
MC_Vref2 [Auto]
Fine Granularity Refresh mode [Auto]
SDRAM Density Per Die [Auto]
SDRAM Banks Per Bank Group [Auto]
SDRAM Bank Groups [Auto]
Dynamic Memory Boost [Disabled]
Realtime Memory Frequency [Disabled]
SA GV [Disabled]
Voltage Monitor [Die Sense]
VRM Initialization Check [Enabled]
CPU Input Voltage Load-line Calibration [Auto]
CPU Load-line Calibration [Level 4:Recommended for OC]
Synch ACDC Loadline with VRM Loadline [Enabled]
CPU Current Capability [Auto]
CPU Current Reporting [Auto]
Core Voltage Suspension [Auto]
CPU VRM Switching Frequency [Auto]
VRM Spread Spectrum [Disabled]
CPU Power Duty Control [Auto]
CPU Power Phase Control [Auto]
CPU Power Thermal Control [125]
CPU Core/Cache Boot Voltage [Auto]
CPU Input Boot Voltage [Auto]
PLL Termination Boot Voltage [Auto]
CPU Standby Boot Voltage [Auto]
Memory Controller Boot Voltage [Auto]
CPU Core Auto Voltage Cap [Auto]
CPU Input Auto Voltage Cap [Auto]
Memory Controller Auto Voltage Cap [Auto]
Fast Throttle Threshold [Auto]
Package Temperature Threshold [Auto]
Regulate Frequency by above Threshold [Auto]
IVR Transmitter VDDQ ICCMAX [Auto]
Unlimited ICCMAX [Auto]
CPU Core/Cache Current Limit Max. [Auto]
Long Duration Package Power Limit [320]
Package Power Time Window [Auto]
Short Duration Package Power Limit [330]
Dual Tau Boost [Disabled]
IA AC Load Line [0.28]
IA DC Load Line [Auto]
IA CEP [Disabled]
SA CEP [Disabled]
IA SoC Iccmax Reactive Protector [Disabled]
Inverse Temperature Dependency Throttle [Auto]
IA VR Voltage Limit [1580]
CPU SVID Support [Auto]
Cache Dynamic OC Switcher [Disabled]
TVB Voltage Optimizations [Disabled]
Enhanced TVB [Disabled]
Overclocking TVB [Disabled]
Overclocking TVB Global Temperature Offset Sign [+]
Overclocking TVB Global Temperature Offset Value [Auto]
Offset Mode Sign 1 [-]
V/F Point 1 Offset [0.01200]
Offset Mode Sign 2 [-]
V/F Point 2 Offset [0.00600]
Offset Mode Sign 3 [+]
V/F Point 3 Offset [0.04500]
Offset Mode Sign 4 [+]
V/F Point 4 Offset [0.04300]
Offset Mode Sign 5 [+]
V/F Point 5 Offset [0.01300]
Offset Mode Sign 6 [-]
V/F Point 6 Offset [0.06200]
Offset Mode Sign 7 [-]
V/F Point 7 Offset [0.11900]
Offset Mode Sign 8 [-]
V/F Point 8 Offset [0.03700]
Offset Mode Sign 9 [-]
V/F Point 9 Offset [0.04400]
Offset Mode Sign 10 [-]
V/F Point 10 Offset [0.04300]
Offset Mode Sign 11 [-]
V/F Point 11 Offset [0.04100]
Initial BCLK Frequency [Auto]
Runtime BCLK OC [Auto]
BCLK Amplitude [Auto]
BCLK Slew Rate [Auto]
BCLK Spread Spectrum [Auto]
Initial PCIE Frequency [Auto]
PCIE/DMI Amplitude [Auto]
PCIE/DMI Slew Rate [Auto]
PCIE/DMI Spread Spectrum [Auto]
Cold Boot PCIE Frequency [Auto]
Realtime Memory Timing [Disabled]
SPD Write Disable [TRUE]
PVD Ratio Threshold [Auto]
SA PLL Frequency Override [Auto]
BCLK TSC HW Fixup [Enabled]
Core Ratio Extension Mode [Disabled]
FLL OC mode [Auto]
UnderVolt Protection [Disabled]
Switch Microcode [Current Microcode]
Xtreme Tweaking [Disabled]
Core PLL Voltage [Auto]
GT PLL Voltage [Auto]
Ring PLL Voltage [Auto]
System Agent PLL Voltage [Auto]
Memory Controller PLL Voltage [Auto]
Efficient-core PLL Voltage [Auto]
CPU 1.8V Small Rail [1.80000]
PLL Termination Voltage [Auto]
CPU Standby Voltage [Auto]
PCH 1.05V Voltage [1.00000]
PCH 0.82V Voltage [0.80000]
CPU Input Voltage Reset Voltage [Auto]
Eventual CPU Input Voltage [Auto]
Eventual Memory Controller Voltage [Auto]
Package Temperature Threshold [Auto]
Regulate Frequency by above Threshold [Auto]
Cooler Efficiency Customize [Keep Training]
Cooler Re-evaluation Algorithm [Normal]
Optimism Scale [100]
Ring Down Bin [Disabled]
Min. CPU Cache Ratio [8]
Max. CPU Cache Ratio [47]
BCLK Aware Adaptive Voltage [Auto]
Actual VRM Core Voltage [Auto]
Global Core SVID Voltage [Auto]
Cache SVID Voltage [Auto]
CPU L2 Voltage [Auto]
CPU System Agent Voltage [Manual Mode]
- CPU System Agent Voltage Override [1.12800]
CPU Input Voltage [Auto]
High DRAM Voltage Mode [Enabled]
DRAM VDD Voltage [1.57000]
DRAM VDDQ Voltage [1.51000]
IVR Transmitter VDDQ Voltage [1.26500]
Memory Controller Voltage [1.36250]
MC Voltage Calculation Voltage Base [Auto]
VDD Calculation Voltage Base [Auto]
PMIC Voltages [Sync All PMICs]
SPD HUB VLDO (1.8V) [1.80000]
SPD HUB VDDIO (1.0V) [1.00000]
DRAM VDD Voltage [1.57000]
DRAM VDDQ Voltage [1.51000]
DRAM VPP Voltage [Auto]
DRAM VDD Switching Frequency [1.50000]
DRAM VDDQ Switching Frequency [1.50000]
DRAM VPP Switching Frequency [1.50000]
DRAM Current Capability [7.87500]
PCI Express Native Power Management [Enabled]
Native ASPM [Disabled]
DMI Link ASPM Control [Disabled]
ASPM [Auto]
L1 Substates [Disabled]
DMI ASPM [Disabled]
DMI Gen3 ASPM [Disabled]
PEG - ASPM [Disabled]
PCI Express Clock Gating [Enabled]
Hardware Prefetcher [Enabled]
Adjacent Cache Line Prefetch [Enabled]
Intel (VMX) Virtualization Technology [Disabled]
Per P-Core Control [Disabled]
Per E-Core Control [Disabled]
Active Performance Cores [All]
Active Efficient Cores [All]
Hyper-Threading [Enabled]
Hyper-Threading of Core 0 [Enabled]
Hyper-Threading of Core 1 [Enabled]
Hyper-Threading of Core 2 [Enabled]
Hyper-Threading of Core 3 [Enabled]
Hyper-Threading of Core 4 [Enabled]
Hyper-Threading of Core 5 [Enabled]
Hyper-Threading of Core 6 [Enabled]
Hyper-Threading of Core 7 [Enabled]
Legacy Game Compatibility Mode [Disabled]
Boot performance mode [Auto]
Intel(R) SpeedStep(tm) [Enabled]
Intel(R) Speed Shift Technology [Enabled]
Intel(R) Turbo Boost Max Technology 3.0 [Enabled]
Turbo Mode [Enabled]
Acoustic Noise Mitigation [Disabled]
CPU C-states [Auto]
Thermal Monitor [Enabled]
Dual Tau Boost [Disabled]
VT-d [Disabled]
Memory Remap [Enabled]
Enable VMD controller [Enabled]
Map PCIe Storage under VMD [Disabled]
Map SATA Controller under VMD [Disabled]
M.2_1 Link Speed [Auto]
PCIEX16(G5)_1 Link Speed [Auto]
PCIEX16(G5)_2 Link Speed [Auto]
PCIEX1(G4) Link Speed [Auto]
PCIEX4(G4) Link Speed [Auto]
M.2_2 Link Speed [Auto]
DIMM.2_1 Link Speed [Auto]
DIMM.2_2 Link Speed [Auto]
SATA Controller(s) [Enabled]
Aggressive LPM Support [Disabled]
SMART Self Test [Enabled]
M.2_3 [Enabled]
M.2_3 Hot Plug [Disabled]
SATA6G_1 [Enabled]
SATA6G_1 Hot Plug [Disabled]
SATA6G_2 [Enabled]
SATA6G_2 Hot Plug [Disabled]
SATA6G_3 [Enabled]
SATA6G_3 Hot Plug [Disabled]
SATA6G_4 [Enabled]
SATA6G_4 Hot Plug [Disabled]
PTT [Enable]
Intel(R) Dynamic Tuning Technology [Disabled]
PCIE Tunneling over USB4 [Enabled]
Discrete Thunderbolt(TM) Support [Disabled]
Security Device Support [Enable]
SHA256 PCR Bank [Enabled]
Pending operation [None]
Platform Hierarchy [Enabled]
Storage Hierarchy [Enabled]
Endorsement Hierarchy [Enabled]
Physical Presence Spec Version [1.3]
Disable Block Sid [Disabled]
USB Host Controller Support [Disabled]
Password protection of Runtime Variables [Enable]
Above 4G Decoding [Enabled]
Resize BAR Support [Enabled]
SR-IOV Support [Disabled]
Legacy USB Support [Enabled]
XHCI Hand-off [Enabled]
SanDisk [Auto]
LAN_U32G2_1 [Enabled]
U32G1_E5 [Enabled]
U32G1_E6 [Enabled]
U32G1_E7 [Enabled]
U32G1_E8 [Enabled]
U32G2X2_C3 [Enabled]
U32G2_5 [Enabled]
U32G2_6 [Enabled]
U32G2_7 [Enabled]
U32G2_P8 [Enabled]
U32G2X2_C9 [Enabled]
U32G1_E1 [Enabled]
U32G1_E2 [Enabled]
U32G1_E3 [Enabled]
U32G1_E4 [Enabled]
Network Stack [Disabled]
Device [N/A]
Restore AC Power Loss [Power Off]
Max Power Saving [Disabled]
ErP Ready [Disabled]
Power On By PCI-E [Disabled]
Power On By RTC [Disabled]
USB Audio [Enabled]
Intel LAN [Enabled]
USB power delivery in Soft Off state (S5) [Disabled]
Connectivity mode (Wi-Fi & Bluetooth) [Disabled]
When system is in working state [All On]
Q-Code LED Function [Auto]
When system is in sleep, hibernate or soft off states [All On]
M.2_2 Configuration [Auto]
ASMedia USB 3.2 Controller_U32G1_E12 [Enabled]
ASMedia USB 3.2 Controller_U32G1_E34 [Enabled]
GNA Device [Disabled]
ASMedia Storage Controller [Enabled]
Windows Hot-plug Notification [Disabled]
ASPM Support [Disabled]
CPU Temperature [Monitor]
CPU Package Temperature [Monitor]
MotherBoard Temperature [Monitor]
VRM Temperature [Monitor]
Chipset Temperature [Monitor]
T_Sensor Temperature [Monitor]
DIMM.2 Sensor 1 Temperature [Monitor]
DIMM.2 Sensor 2 Temperature [Monitor]
Water In T Sensor Temperature [Monitor]
Water Out T Sensor Temperature [Monitor]
DIMM A1 Temperature [Monitor]
DIMM B1 Temperature [Monitor]
CPU Fan Speed [Monitor]
CPU Optional Fan Speed [Monitor]
Chassis Fan 1 Speed [Monitor]
Chassis Fan 2 Speed [Monitor]
Chassis Fan 3 Speed [Monitor]
Water Pump+ Speed [Monitor]
AIO Pump Speed [Monitor]
Flow Rate [Monitor]
CPU Core Voltage [Monitor]
12V Voltage [Monitor]
5V Voltage [Monitor]
3.3V Voltage [Monitor]
Memory Controller Voltage [Monitor]
CPU Fan Q-Fan Control [DC Mode]
CPU Fan Profile [Standard]
CPU Fan Q-Fan Source [CPU]
CPU Fan Step Up [Level 0]
CPU Fan Step Down [Level 4]
CPU Fan Speed Low Limit [200 RPM]
Chassis Fan 1 Q-Fan Control [Auto Detect]
Chassis Fan 1 Profile [Standard]
Chassis Fan 1 Q-Fan Source [CPU]
Chassis Fan 1 Step Up [Level 0]
Chassis Fan 1 Step Down [Level 0]
Chassis Fan 1 Speed Low Limit [200 RPM]
Chassis Fan 2 Q-Fan Control [PWM Mode]
Chassis Fan 2 Profile [Standard]
Chassis Fan 2 Q-Fan Source [Chipset]
Chassis Fan 2 Step Up [Level 0]
Chassis Fan 2 Step Down [Level 4]
Chassis Fan 2 Speed Low Limit [200 RPM]
Chassis Fan 3 Q-Fan Control [DC Mode]
Chassis Fan 3 Profile [Silent]
Chassis Fan 3 Q-Fan Source [CPU]
Chassis Fan 3 Step Up [Level 0]
Chassis Fan 3 Step Down [Level 0]
Chassis Fan 3 Speed Low Limit [200 RPM]
Water Pump+ Q-Fan Control [PWM Mode]
Water Pump+ Profile [Manual]
Water Pump+ Q-Fan Source [CPU]
Water Pump+ Step Up [Level 0]
Water Pump+ Step Down [Level 4]
Water Pump+ Speed Low Limit [Ignore]
Water Pump+ Point4 Temperature [70]
Water Pump+ Point4 Duty Cycle (%) [100]
Water Pump+ Point3 Temperature [50]
Water Pump+ Point3 Duty Cycle (%) [85]
Water Pump+ Point2 Temperature [40]
Water Pump+ Point2 Duty Cycle (%) [80]
Water Pump+ Point1 Temperature [25]
Water Pump+ Point1 Duty Cycle (%) [60]
AIO Pump Q-Fan Control [Auto Detect]
AIO Pump Profile [Full Speed]
CPU Temperature LED Switch [Enabled]
Launch CSM [Disabled]
OS Type [Other OS]
Secure Boot Mode [Custom]
Fast Boot [Disabled]
Boot Logo Display [Auto]
POST Delay Time [3 sec]
Bootup NumLock State [On]
Wait For 'F1' If Error [Enabled]
Option ROM Messages [Force BIOS]
Interrupt 19 Capture [Disabled]
AMI Native NVMe Driver Support [Enabled]
Setup Mode [Advanced Mode]
Boot Sector (MBR/GPT) Recovery Policy [Local User Control]
Next Boot Recovery Action [Skip]
BIOS Image Rollback Support [Enabled]
Publish HII Resources [Disabled]
Flexkey [Safe Boot]
Setup Animator [Disabled]
Load from Profile [6]
Profile Name [8000C34]
Save to Profile [6]
DIMM Slot Number [DIMM_A1]
Download & Install ARMOURY CRATE app [Disabled]
Download & Install MyASUS service & app [Disabled]
Ai Overclock Tuner [Manual]
BCLK Frequency [100.0000]
PCIE Frequency [100.0000]
Intel(R) Adaptive Boost Technology [Auto]
ASUS MultiCore Enhancement [Enabled – Remove All limits (90°C)]
SVID Behavior [Trained]
BCLK Frequency : DRAM Frequency Ratio [100:100]
Memory Controller : DRAM Frequency Ratio [1:2]
DRAM Frequency [DDR5-8000MHz]
Performance Core Ratio [By Core Usage]
1-Core Ratio Limit [57]
2-Core Ratio Limit [57]
3-Core Ratio Limit [56]
4-Core Ratio Limit [56]
5-Core Ratio Limit [55]
6-Core Ratio Limit [55]
7-Core Ratio Limit [54]
8-Core Ratio Limit [54]
Performance Core0 Specific Ratio Limit [Auto]
Performance Core0 specific Voltage [Auto]
Performance Core1 Specific Ratio Limit [Auto]
Performance Core1 specific Voltage [Auto]
*Performance Core2 Specific Ratio Limit [Auto]
Performance Core2 specific Voltage [Auto]
*Performance Core3 Specific Ratio Limit [Auto]
Performance Core3 specific Voltage [Auto]
Performance Core4 Specific Ratio Limit [Auto]
Performance Core4 specific Voltage [Auto]
Performance Core5 Specific Ratio Limit [Auto]
Performance Core5 specific Voltage [Auto]
Performance Core6 Specific Ratio Limit [Auto]
Performance Core6 specific Voltage [Auto]
Performance Core7 Specific Ratio Limit [Auto]
Performance Core7 specific Voltage [Auto]
Efficient Core Ratio [By Core Usage]
Efficient Turbo Ratio Limit 1 [43]
Efficient Turbo Ratio Cores 1 [Auto]
Efficient Core Group0 Specific Ratio Limit [Auto]
Efficient Core Group0 specific Voltage [Auto]
Efficient Core Group1 Specific Ratio Limit [Auto]
Efficient Core Group1 specific Voltage [Auto]
Efficient Core Group2 Specific Ratio Limit [Auto]
Efficient Core Group2 specific Voltage [Auto]
Efficient Core Group3 Specific Ratio Limit [Auto]
Efficient Core Group3 specific Voltage [Auto]
AVX2 [Auto]
AVX2 Ratio Offset to per-core Ratio Limit [Auto]
AVX2 Voltage Guardband Scale Factor [Auto]
Maximus Tweak [Mode 2]
DRAM CAS# Latency [34]
DRAM RAS# to CAS# Delay Read [45]
DRAM RAS# to CAS# Delay Write [25]
DRAM RAS# PRE Time [45]
DRAM RAS# ACT Time [61]
DRAM Command Rate [2N]
DRAM RAS# to RAS# Delay L [8]
DRAM RAS# to RAS# Delay S [8]
DRAM REF Cycle Time 2 [480]
DRAM REF Cycle Time Same Bank [448]
DRAM Refresh Interval [262143]
DRAM WRITE Recovery Time [24]
DRAM READ to PRE Time [12]
DRAM FOUR ACT WIN Time [32]
DRAM WRITE to READ Delay L [16]
DRAM WRITE to READ Delay S [4]
DRAM CKE Minimum Pulse Width [20]
DRAM Write Latency [32]
Ctl0 dqvrefup [170]
Ctl0 dqvrefdn [88]
Ctl0 dqodtvrefup [Auto]
Ctl0 dqodtvrefdn [Auto]
Ctl1 cmdvrefup [Auto]
Ctl1 ctlvrefup [Auto]
Ctl1 clkvrefup [Auto]
Ctl1 ckecsvrefup [Auto]
Ctl2 cmdvrefdn [Auto]
Ctl2 ctlvrefdn [Auto]
Ctl2 clkvrefdn [Auto]
Read Equalization RxEq Start Sign [-]
Read Equalization RxEq Start [Auto]
Read Equalization RxEq Stop Sign [-]
Read Equalization RxEq Stop [Auto]
ODT_READ_DURATION [Auto]
ODT_READ_DELAY [Auto]
ODT_WRITE_DURATION [Auto]
ODT_WRITE_DELAY [Auto]
DQ RTT WR [40 DRAM Clock]
DQ RTT NOM RD [40 DRAM Clock]
DQ RTT NOM WR [34 DRAM Clock]
DQ RTT PARK [34 DRAM Clock]
DQ RTT PARK DQS [34 DRAM Clock]
GroupA CA ODT [240 DRAM Clock]
GroupA CS ODT [0 DRAM Clock]
GroupA CK ODT [0 DRAM Clock]
GroupB CA ODT [60 DRAM Clock]
GroupB CS ODT [40 DRAM Clock]
GroupB CK ODT [40 DRAM Clock]
Pull-up Output Driver Impedance [48 DRAM Clock]
Pull-Down Output Driver Impedance [40 DRAM Clock]
DQ RTT WR [40 DRAM Clock]
DQ RTT NOM RD [40 DRAM Clock]
DQ RTT NOM WR [34 DRAM Clock]
DQ RTT PARK [34 DRAM Clock]
DQ RTT PARK DQS [34 DRAM Clock]
GroupA CA ODT [240 DRAM Clock]
GroupA CS ODT [0 DRAM Clock]
GroupA CK ODT [0 DRAM Clock]
GroupB CA ODT [60 DRAM Clock]
GroupB CS ODT [40 DRAM Clock]
GroupB CK ODT [40 DRAM Clock]
Pull-up Output Driver Impedance [40 DRAM Clock]
Pull-Down Output Driver Impedance [48 DRAM Clock]
Round Trip Latency Init Value MC0 CHA [Auto]
Round Trip Latency Max Value MC0 CHA [Auto]
Round Trip Latency Offset Value Mode Sign MC0 CHA [-]
Round Trip Latency Offset Value MC0 CHA [Auto]
Round Trip Latency Init Value MC0 CHB [Auto]
Round Trip Latency Max Value MC0 CHB [Auto]
Round Trip Latency Offset Value Mode Sign MC0 CHB [-]
Round Trip Latency Offset Value MC0 CHB [Auto]
Round Trip Latency Init Value MC1 CHA [Auto]
Round Trip Latency Max Value MC1 CHA [Auto]
Round Trip Latency Offset Value Mode Sign MC1 CHA [-]
Round Trip Latency Offset Value MC1 CHA [Auto]
Round Trip Latency Init Value MC1 CHB [Auto]
Round Trip Latency Max Value MC1 CHB [Auto]
Round Trip Latency Offset Value Mode Sign MC1 CHB [-]
Round Trip Latency Offset Value MC1 CHB [Auto]
Round Trip Latency MC0 CHA R0 [Auto]
Round Trip Latency MC0 CHA R1 [Auto]
Round Trip Latency MC0 CHA R2 [0]
Round Trip Latency MC0 CHA R3 [0]
Round Trip Latency MC0 CHA R4 [0]
Round Trip Latency MC0 CHA R5 [0]
Round Trip Latency MC0 CHA R6 [0]
Round Trip Latency MC0 CHA R7 [0]
Round Trip Latency MC0 CHB R0 [Auto]
Round Trip Latency MC0 CHB R1 [Auto]
Round Trip Latency MC0 CHB R2 [0]
Round Trip Latency MC0 CHB R3 [0]
Round Trip Latency MC0 CHB R4 [0]
Round Trip Latency MC0 CHB R5 [0]
Round Trip Latency MC0 CHB R6 [0]
Round Trip Latency MC0 CHB R7 [0]
Round Trip Latency MC1 CHA R0 [Auto]
Round Trip Latency MC1 CHA R1 [Auto]
Round Trip Latency MC1 CHA R2 [0]
Round Trip Latency MC1 CHA R3 [0]
Round Trip Latency MC1 CHA R4 [0]
Round Trip Latency MC1 CHA R5 [0]
Round Trip Latency MC1 CHA R6 [0]
Round Trip Latency MC1 CHA R7 [0]
Round Trip Latency MC1 CHB R0 [Auto]
Round Trip Latency MC1 CHB R1 [Auto]
Round Trip Latency MC1 CHB R2 [0]
Round Trip Latency MC1 CHB R3 [0]
Round Trip Latency MC1 CHB R4 [0]
Round Trip Latency MC1 CHB R5 [0]
Round Trip Latency MC1 CHB R6 [0]
Round Trip Latency MC1 CHB R7 [0]
Early Command Training [Auto]
SenseAmp Offset Training [Auto]
Early ReadMPR Timing Centering 2D [Auto]
Read MPR Training [Auto]
Receive Enable Training [Auto]
Jedec Write Leveling [Auto]
Early Write Time Centering 2D [Auto]
Early Read Time Centering 2D [Auto]
Write Timing Centering 1D [Auto]
Write Voltage Centering 1D [Auto]
Read Timing Centering 1D [Auto]
Read Timing Centering with JR [Auto]
Dimm ODT Training* [Disabled]
Max RTT_WR [ODT Off]
DIMM RON Training* [Disabled]
Write Drive Strength/Equalization 2D* [Auto]
Write Slew Rate Training* [Auto]
Read ODT Training* [Disabled]
Comp Optimization Training [Auto]
Read Equalization Training* [Auto]
Read Amplifier Training* [Auto]
Write Timing Centering 2D [Auto]
Read Timing Centering 2D [Auto]
Command Voltage Centering [Auto]
Early Command Voltage Centering [Auto]
Write Voltage Centering 2D [Auto]
Read Voltage Centering 2D [Auto]
Late Command Training [Auto]
Round Trip Latency [Auto]
Turn Around Timing Training [Auto]
CMD CTL CLK Slew Rate [Auto]
CMD/CTL DS & E 2D [Auto]
Read Voltage Centering 1D [Auto]
TxDqTCO Comp Training* [Auto]
ClkTCO Comp Training* [Auto]
TxDqsTCO Comp Training* [Auto]
VccDLL Bypass Training [Auto]
CMD/CTL Drive Strength Up/Dn 2D [Auto]
DIMM CA ODT Training [Auto]
PanicVttDnLp Training* [Auto]
Read Vref Decap Training* [Auto]
Vddq Training [Disabled]
Duty Cycle Correction Training [Auto]
Periodic DCC [Auto]
Rank Margin Tool Per Bit [Auto]
DIMM DFE Training [Auto]
EARLY DIMM DFE Training [Auto]
Tx Dqs Dcc Training [Auto]
DRAM DCA Training [Auto]
Write Driver Strength Training [Auto]
Rank Margin Tool [Auto]
Memory Test [Auto]
DIMM SPD Alias Test [Auto]
Receive Enable Centering 1D [Auto]
Retrain Margin Check [Auto]
Write Drive Strength Up/Dn independently [Auto]
LPDDR DqDqs Re-Training [Auto]
Margin Check Limit [Disabled]
tRDRD_sg_Training [Auto]
tRDRD_sg_Runtime [16]
tRDRD_dg_Training [Auto]
tRDRD_dg_Runtime [8]
tRDWR_sg [20]
tRDWR_dg [20]
tWRWR_sg [16]
tWRWR_dg [8]
tWRRD_sg [Auto]
tWRRD_dg [Auto]
tRDRD_dr [1]
tRDRD_dd [0]
tRDWR_dr [1]
tRDWR_dd [0]
tWRWR_dr [1]
tWRWR_dd [0]
tWRRD_dr [1]
tWRRD_dd [0]
tRPRE [Auto]
tWPRE [Auto]
tWPOST [Auto]
tWRPRE [Auto]
tPRPDEN [Auto]
tRDPDEN [Auto]
tWRPDEN [Auto]
tCPDED [Auto]
tREFIX9 [Auto]
Ref Interval [Auto]
tXPDLL [Auto]
tXP [Auto]
tPPD [2]
tCCD_L_tDLLK [Auto]
tZQCAL [Auto]
tZQCS [Auto]
OREF_RI [Auto]
Refresh Watermarks [High]
Refresh Hp Wm [Auto]
Refresh Panic Wm [Auto]
Refresh Abr Release [Auto]
tXSDLL [Auto]
tZQOPER [Auto]
tMOD [Auto]
CounttREFIWhileRefEn [Auto]
HPRefOnMRS [Auto]
SRX Ref Debits [Auto]
RAISE BLK WAIT [Auto]
Ref Stagger En [Auto]
Ref Stagger Mode [Auto]
Disable Stolen Refresh [Auto]
En Ref Type Display [Auto]
Trefipulse Stagger Disable [Auto]
tRPab ext [Auto]
derating ext [Auto]
Allow 2cyc B2B LPDDR [Auto]
tCSH [Auto]
tCSL [Auto]
powerdown Enable [Auto]
idle length [Auto]
raise cke after exit latency [Auto]
powerdown latency [Auto]
powerdown length [Auto]
selfrefresh latency [Auto]
selfrefresh length [Auto]
ckevalid length [Auto]
ckevalid enable [Auto]
idle enable [Auto]
selfrefresh enable [Auto]
Address mirror [Auto]
no gear4 param divide [Auto]
x8 device [Auto]
no gear2 param divide [Auto]
ddr 1dpc split ranks on subch [Auto]
write0 enable [Auto]
MultiCycCmd [Auto]
WCKDiffLowInIdle [Auto]
PBR Disable [Auto]
PBR OOO Dis [Auto]
PBR Disable on hot [Auto]
PBR Exit on Idle Cnt [Auto]
tXSR [Auto]
Dec tCWL [Auto]
Add tCWL [Auto]
Add 1Qclk delay [Auto]
MRC Fast Boot [Disabled]
MCH Full Check [Auto]
Mem Over Clock Fail Count [3]
Training Profile [ASUS User Profile]
RxDfe [Enabled]
Mrc Training Loop Count [3]
DRAM CLK Period [Auto]
Dll_bwsel [Auto]
Controller 0, Channel 0 Control [Enabled]
Controller 0, Channel 1 Control [Enabled]
Controller 1, Channel 0 Control [Enabled]
Controller 1, Channel 1 Control [Enabled]
MC_Vref0 [Auto]
MC_Vref1 [Auto]
MC_Vref2 [Auto]
Fine Granularity Refresh mode [Auto]
SDRAM Density Per Die [Auto]
SDRAM Banks Per Bank Group [Auto]
SDRAM Bank Groups [Auto]
Dynamic Memory Boost [Disabled]
Realtime Memory Frequency [Disabled]
SA GV [Disabled]
Voltage Monitor [Die Sense]
VRM Initialization Check [Enabled]
CPU Input Voltage Load-line Calibration [Auto]
CPU Load-line Calibration [Level 4:Recommended for OC]
Synch ACDC Loadline with VRM Loadline [Enabled]
CPU Current Capability [Auto]
CPU Current Reporting [Auto]
Core Voltage Suspension [Auto]
CPU VRM Switching Frequency [Auto]
VRM Spread Spectrum [Disabled]
CPU Power Duty Control [Auto]
CPU Power Phase Control [Auto]
CPU Power Thermal Control [125]
CPU Core/Cache Boot Voltage [Auto]
CPU Input Boot Voltage [Auto]
PLL Termination Boot Voltage [Auto]
CPU Standby Boot Voltage [Auto]
Memory Controller Boot Voltage [Auto]
CPU Core Auto Voltage Cap [Auto]
CPU Input Auto Voltage Cap [Auto]
Memory Controller Auto Voltage Cap [Auto]
Fast Throttle Threshold [Auto]
Package Temperature Threshold [Auto]
Regulate Frequency by above Threshold [Auto]
IVR Transmitter VDDQ ICCMAX [Auto]
Unlimited ICCMAX [Auto]
CPU Core/Cache Current Limit Max. [Auto]
Long Duration Package Power Limit [320]
Package Power Time Window [Auto]
Short Duration Package Power Limit [330]
Dual Tau Boost [Disabled]
IA AC Load Line [0.28]
IA DC Load Line [Auto]
IA CEP [Disabled]
SA CEP [Disabled]
IA SoC Iccmax Reactive Protector [Disabled]
Inverse Temperature Dependency Throttle [Auto]
IA VR Voltage Limit [1580]
CPU SVID Support [Auto]
Cache Dynamic OC Switcher [Disabled]
TVB Voltage Optimizations [Disabled]
Enhanced TVB [Disabled]
Overclocking TVB [Disabled]
Overclocking TVB Global Temperature Offset Sign [+]
Overclocking TVB Global Temperature Offset Value [Auto]
Offset Mode Sign 1 [-]
V/F Point 1 Offset [0.01200]
Offset Mode Sign 2 [-]
V/F Point 2 Offset [0.00600]
Offset Mode Sign 3 [+]
V/F Point 3 Offset [0.04500]
Offset Mode Sign 4 [+]
V/F Point 4 Offset [0.04300]
Offset Mode Sign 5 [+]
V/F Point 5 Offset [0.01300]
Offset Mode Sign 6 [-]
V/F Point 6 Offset [0.06200]
Offset Mode Sign 7 [-]
V/F Point 7 Offset [0.11900]
Offset Mode Sign 8 [-]
V/F Point 8 Offset [0.03700]
Offset Mode Sign 9 [-]
V/F Point 9 Offset [0.04400]
Offset Mode Sign 10 [-]
V/F Point 10 Offset [0.04300]
Offset Mode Sign 11 [-]
V/F Point 11 Offset [0.04100]
Initial BCLK Frequency [Auto]
Runtime BCLK OC [Auto]
BCLK Amplitude [Auto]
BCLK Slew Rate [Auto]
BCLK Spread Spectrum [Auto]
Initial PCIE Frequency [Auto]
PCIE/DMI Amplitude [Auto]
PCIE/DMI Slew Rate [Auto]
PCIE/DMI Spread Spectrum [Auto]
Cold Boot PCIE Frequency [Auto]
Realtime Memory Timing [Disabled]
SPD Write Disable [TRUE]
PVD Ratio Threshold [Auto]
SA PLL Frequency Override [Auto]
BCLK TSC HW Fixup [Enabled]
Core Ratio Extension Mode [Disabled]
FLL OC mode [Auto]
UnderVolt Protection [Disabled]
Switch Microcode [Current Microcode]
Xtreme Tweaking [Disabled]
Core PLL Voltage [Auto]
GT PLL Voltage [Auto]
Ring PLL Voltage [Auto]
System Agent PLL Voltage [Auto]
Memory Controller PLL Voltage [Auto]
Efficient-core PLL Voltage [Auto]
CPU 1.8V Small Rail [1.80000]
PLL Termination Voltage [Auto]
CPU Standby Voltage [Auto]
PCH 1.05V Voltage [1.00000]
PCH 0.82V Voltage [0.80000]
CPU Input Voltage Reset Voltage [Auto]
Eventual CPU Input Voltage [Auto]
Eventual Memory Controller Voltage [Auto]
Package Temperature Threshold [Auto]
Regulate Frequency by above Threshold [Auto]
Cooler Efficiency Customize [Keep Training]
Cooler Re-evaluation Algorithm [Normal]
Optimism Scale [100]
Ring Down Bin [Disabled]
Min. CPU Cache Ratio [8]
Max. CPU Cache Ratio [47]
BCLK Aware Adaptive Voltage [Auto]
Actual VRM Core Voltage [Auto]
Global Core SVID Voltage [Auto]
Cache SVID Voltage [Auto]
CPU L2 Voltage [Auto]
CPU System Agent Voltage [Manual Mode]
- CPU System Agent Voltage Override [1.12800]
CPU Input Voltage [Auto]
High DRAM Voltage Mode [Enabled]
DRAM VDD Voltage [1.57000]
DRAM VDDQ Voltage [1.51000]
IVR Transmitter VDDQ Voltage [1.26500]
Memory Controller Voltage [1.36250]
MC Voltage Calculation Voltage Base [Auto]
VDD Calculation Voltage Base [Auto]
PMIC Voltages [Sync All PMICs]
SPD HUB VLDO (1.8V) [1.80000]
SPD HUB VDDIO (1.0V) [1.00000]
DRAM VDD Voltage [1.57000]
DRAM VDDQ Voltage [1.51000]
DRAM VPP Voltage [Auto]
DRAM VDD Switching Frequency [1.50000]
DRAM VDDQ Switching Frequency [1.50000]
DRAM VPP Switching Frequency [1.50000]
DRAM Current Capability [7.87500]
PCI Express Native Power Management [Enabled]
Native ASPM [Disabled]
DMI Link ASPM Control [Disabled]
ASPM [Auto]
L1 Substates [Disabled]
DMI ASPM [Disabled]
DMI Gen3 ASPM [Disabled]
PEG - ASPM [Disabled]
PCI Express Clock Gating [Enabled]
Hardware Prefetcher [Enabled]
Adjacent Cache Line Prefetch [Enabled]
Intel (VMX) Virtualization Technology [Disabled]
Per P-Core Control [Disabled]
Per E-Core Control [Disabled]
Active Performance Cores [All]
Active Efficient Cores [All]
Hyper-Threading [Enabled]
Hyper-Threading of Core 0 [Enabled]
Hyper-Threading of Core 1 [Enabled]
Hyper-Threading of Core 2 [Enabled]
Hyper-Threading of Core 3 [Enabled]
Hyper-Threading of Core 4 [Enabled]
Hyper-Threading of Core 5 [Enabled]
Hyper-Threading of Core 6 [Enabled]
Hyper-Threading of Core 7 [Enabled]
Legacy Game Compatibility Mode [Disabled]
Boot performance mode [Auto]
Intel(R) SpeedStep(tm) [Enabled]
Intel(R) Speed Shift Technology [Enabled]
Intel(R) Turbo Boost Max Technology 3.0 [Enabled]
Turbo Mode [Enabled]
Acoustic Noise Mitigation [Disabled]
CPU C-states [Auto]
Thermal Monitor [Enabled]
Dual Tau Boost [Disabled]
VT-d [Disabled]
Memory Remap [Enabled]
Enable VMD controller [Enabled]
Map PCIe Storage under VMD [Disabled]
Map SATA Controller under VMD [Disabled]
M.2_1 Link Speed [Auto]
PCIEX16(G5)_1 Link Speed [Auto]
PCIEX16(G5)_2 Link Speed [Auto]
PCIEX1(G4) Link Speed [Auto]
PCIEX4(G4) Link Speed [Auto]
M.2_2 Link Speed [Auto]
DIMM.2_1 Link Speed [Auto]
DIMM.2_2 Link Speed [Auto]
SATA Controller(s) [Enabled]
Aggressive LPM Support [Disabled]
SMART Self Test [Enabled]
M.2_3 [Enabled]
M.2_3 Hot Plug [Disabled]
SATA6G_1 [Enabled]
SATA6G_1 Hot Plug [Disabled]
SATA6G_2 [Enabled]
SATA6G_2 Hot Plug [Disabled]
SATA6G_3 [Enabled]
SATA6G_3 Hot Plug [Disabled]
SATA6G_4 [Enabled]
SATA6G_4 Hot Plug [Disabled]
PTT [Enable]
Intel(R) Dynamic Tuning Technology [Disabled]
PCIE Tunneling over USB4 [Enabled]
Discrete Thunderbolt(TM) Support [Disabled]
Security Device Support [Enable]
SHA256 PCR Bank [Enabled]
Pending operation [None]
Platform Hierarchy [Enabled]
Storage Hierarchy [Enabled]
Endorsement Hierarchy [Enabled]
Physical Presence Spec Version [1.3]
Disable Block Sid [Disabled]
USB Host Controller Support [Disabled]
Password protection of Runtime Variables [Enable]
Above 4G Decoding [Enabled]
Resize BAR Support [Enabled]
SR-IOV Support [Disabled]
Legacy USB Support [Enabled]
XHCI Hand-off [Enabled]
SanDisk [Auto]
LAN_U32G2_1 [Enabled]
U32G1_E5 [Enabled]
U32G1_E6 [Enabled]
U32G1_E7 [Enabled]
U32G1_E8 [Enabled]
U32G2X2_C3 [Enabled]
U32G2_5 [Enabled]
U32G2_6 [Enabled]
U32G2_7 [Enabled]
U32G2_P8 [Enabled]
U32G2X2_C9 [Enabled]
U32G1_E1 [Enabled]
U32G1_E2 [Enabled]
U32G1_E3 [Enabled]
U32G1_E4 [Enabled]
Network Stack [Disabled]
Device [N/A]
Restore AC Power Loss [Power Off]
Max Power Saving [Disabled]
ErP Ready [Disabled]
Power On By PCI-E [Disabled]
Power On By RTC [Disabled]
USB Audio [Enabled]
Intel LAN [Enabled]
USB power delivery in Soft Off state (S5) [Disabled]
Connectivity mode (Wi-Fi & Bluetooth) [Disabled]
When system is in working state [All On]
Q-Code LED Function [Auto]
When system is in sleep, hibernate or soft off states [All On]
M.2_2 Configuration [Auto]
ASMedia USB 3.2 Controller_U32G1_E12 [Enabled]
ASMedia USB 3.2 Controller_U32G1_E34 [Enabled]
GNA Device [Disabled]
ASMedia Storage Controller [Enabled]
Windows Hot-plug Notification [Disabled]
ASPM Support [Disabled]
CPU Temperature [Monitor]
CPU Package Temperature [Monitor]
MotherBoard Temperature [Monitor]
VRM Temperature [Monitor]
Chipset Temperature [Monitor]
T_Sensor Temperature [Monitor]
DIMM.2 Sensor 1 Temperature [Monitor]
DIMM.2 Sensor 2 Temperature [Monitor]
Water In T Sensor Temperature [Monitor]
Water Out T Sensor Temperature [Monitor]
DIMM A1 Temperature [Monitor]
DIMM B1 Temperature [Monitor]
CPU Fan Speed [Monitor]
CPU Optional Fan Speed [Monitor]
Chassis Fan 1 Speed [Monitor]
Chassis Fan 2 Speed [Monitor]
Chassis Fan 3 Speed [Monitor]
Water Pump+ Speed [Monitor]
AIO Pump Speed [Monitor]
Flow Rate [Monitor]
CPU Core Voltage [Monitor]
12V Voltage [Monitor]
5V Voltage [Monitor]
3.3V Voltage [Monitor]
Memory Controller Voltage [Monitor]
CPU Fan Q-Fan Control [DC Mode]
CPU Fan Profile [Standard]
CPU Fan Q-Fan Source [CPU]
CPU Fan Step Up [Level 0]
CPU Fan Step Down [Level 4]
CPU Fan Speed Low Limit [200 RPM]
Chassis Fan 1 Q-Fan Control [Auto Detect]
Chassis Fan 1 Profile [Standard]
Chassis Fan 1 Q-Fan Source [CPU]
Chassis Fan 1 Step Up [Level 0]
Chassis Fan 1 Step Down [Level 0]
Chassis Fan 1 Speed Low Limit [200 RPM]
Chassis Fan 2 Q-Fan Control [PWM Mode]
Chassis Fan 2 Profile [Standard]
Chassis Fan 2 Q-Fan Source [Chipset]
Chassis Fan 2 Step Up [Level 0]
Chassis Fan 2 Step Down [Level 4]
Chassis Fan 2 Speed Low Limit [200 RPM]
Chassis Fan 3 Q-Fan Control [DC Mode]
Chassis Fan 3 Profile [Silent]
Chassis Fan 3 Q-Fan Source [CPU]
Chassis Fan 3 Step Up [Level 0]
Chassis Fan 3 Step Down [Level 0]
Chassis Fan 3 Speed Low Limit [200 RPM]
Water Pump+ Q-Fan Control [PWM Mode]
Water Pump+ Profile [Manual]
Water Pump+ Q-Fan Source [CPU]
Water Pump+ Step Up [Level 0]
Water Pump+ Step Down [Level 4]
Water Pump+ Speed Low Limit [Ignore]
Water Pump+ Point4 Temperature [70]
Water Pump+ Point4 Duty Cycle (%) [100]
Water Pump+ Point3 Temperature [50]
Water Pump+ Point3 Duty Cycle (%) [85]
Water Pump+ Point2 Temperature [40]
Water Pump+ Point2 Duty Cycle (%) [80]
Water Pump+ Point1 Temperature [25]
Water Pump+ Point1 Duty Cycle (%) [60]
AIO Pump Q-Fan Control [Auto Detect]
AIO Pump Profile [Full Speed]
CPU Temperature LED Switch [Enabled]
Launch CSM [Disabled]
OS Type [Other OS]
Secure Boot Mode [Custom]
Fast Boot [Disabled]
Boot Logo Display [Auto]
POST Delay Time [3 sec]
Bootup NumLock State [On]
Wait For 'F1' If Error [Enabled]
Option ROM Messages [Force BIOS]
Interrupt 19 Capture [Disabled]
AMI Native NVMe Driver Support [Enabled]
Setup Mode [Advanced Mode]
Boot Sector (MBR/GPT) Recovery Policy [Local User Control]
Next Boot Recovery Action [Skip]
BIOS Image Rollback Support [Enabled]
Publish HII Resources [Disabled]
Flexkey [Safe Boot]
Setup Animator [Disabled]
Load from Profile [6]
Profile Name [8000C34]
Save to Profile [6]
DIMM Slot Number [DIMM_A1]
Download & Install ARMOURY CRATE app [Disabled]
Download & Install MyASUS service & app [Disabled]
TM5 ist noch mit 1.27V TX gelaufen, Y Cruncher schon 1.265V. Ich glaube spielt keine Rolle. Paar Spannungswerte waren fixiert, aber heute habe ich auf auto zuerueckgestellt.
Zum vergleichen, hier ist 8000C36
@Veii:
"Bitte exportiere mir wieder dein Bios.cfg mit sce
"Hier ist das alte 6 Std. lang Y+BIOS
"CAS + tBL/2 + OdtOnLat (1) = tRdPdEN 『powerdown enabled』
CAS + tBL/2 = tRdPRE『precharge enabled』 *********** es finde ich nicht **********
CWL (CAS-2) + tBL/2 + tWR (CPU) + OdtOnLat (PhyDly =1) = tWrPdEN
CWL (CAS-2) + tBL/2 + tWR (CPU) = tWrPRE"
Ich hoffe, dass ich alles gut und richtig verstanden:
So habe ich mit 8200 angefangen
TM5 OK (Vielleicht, habe ich 25 Zyklen nicht überprüft), aber Y nicht.
Alleine VT3 und HT aus mir intressiere nicht, leider noch nicht Y stabil.
Anhänge
Vergiss Formeln, einfach runter drehen bis er nicht mehr bootet oder schnell Fehler schmeißt und dann wieder 20 drauf. RFC und rfcpb getrennt testen.
640 / 416 könnte laufen oder 672 / 448.
zebra_hun
Profi
C34 vs C36, Ratio ist nicht so gut.
Ueber 300 min fps ist doch gut. Aber C36 million mal besser.
Edit:
Bonus some bench without OC, alle Kerne und HT an.
Allcore 54x (2k boost 57x) P, 43E, 47R, 24/7 Settings.
Ueber 300 min fps ist doch gut. Aber C36 million mal besser.
Edit:
Bonus some bench without OC, alle Kerne und HT an.
Allcore 54x (2k boost 57x) P, 43E, 47R, 24/7 Settings.
Anhänge
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RFC2 ist RFCab (between) all bank, nur im FineGranularity Modus
RFCpb/sb geschieht innerhalb der Bank
Die Bank Anzahl bezieht sich auf 32.
Jede ROW wird bei einem ACT timing (von der MC Seite), komplett aktiv
Jede dieser ROWs kann nur einzeln aktiv bleiben. Single Command per Strobe ! (UDIMM)
Nach dem diese offen war , die Spannung von jeder 1Transistor1Capacitor Zelle ~ an die Wordline weitergibt (Y-Axis)
Diese durch SenseAMP (da 65536 Rows eine recht große Distanz sind) ~ verstärkt entladed oder rückladet;
Wird diese ROW als "genutzt" markiert und mit dem selben Timing (Read+AutoPrecharge, Read, then Precharge command) ~ geschlossen
All diese 8192x65536 Zellen, sind eine einzelne Bank.
Ram geht nicht von einer Bank hinnein und benützt all diese Rows eine nach der anderen
Nein nein, das ist aufwending wenn man jedes mal CAS (column access) & RAS (row access) commands senden muss.
Die CPU und der RAM nun selber, springt zwischen banks und bank groups
Bank groups sind vernetzt und können darauf nahezu ohne delay zugegriffen werden.
Es springt zwischen den obersten Teil der Bank, bis alle Banks durch sind - bevor es den RFCpb/sb oder ab & REFIab/REFpb ausführt.
RFCsb/pb (same bank)
Braucht nicht sehr lange zu sein, da es sich um die selbe Bank handelt und zwischen dem oberen und nachfolgendem Zugriff genug Zeit vergangen ist
SameBank delay logisch hängt davon an wie weit die Collum ist auf der Zugegriffen werden kann.
Bei 2GB ICs (16gb) ist das ein 16er layout
Bei 3gb ICs (24gb) ist das ein 24er layout
Da man sonnst nicht auf diese Dichte kommt.
Die Banks der ICs sind einfach breiter und dicker.
Da diese Dicker sind werden zb auch _L timings
Wie RRD_L (read to read/pre) same bankgroup ~ logisch länger brauchen.
Größere Distanz.
EDIT:
Micron's rohe Erklärung & specifications
Im Durchschnitt (gerechnet dank tRET) ~160ns für FineGranularity Mode tRFCab & 130ns für RFCpb/REFsb/RFCsb (AMD nennt es anders)
Reale Zeit benötigt, abweichend von dem Arch design und Thermal Stability.
Alles nur ein Richtwert, (S)DRAM arbeitet nicht auf Worldclock mit ns Werten. Alles nur einfach lesbare gerundete Werte;
RAM arbeitet auf picosec/hz (nCK integers, abweichend zu MT/s clock)
1ps = 1e9 ms . 1 & 9*0 = 1 000 000 000ms
Und wenn du das nun verstehst
Solltest du verstehen wie man bei DDR5 auf RFCab steps (32) ~ all banks , 32 banks
Und RFCpb/sb 16/24 (same bank, each bank, maximal active 16 wide row)
Innerhalb REFIab 65536 (maximal zugreifbare individuelle ROWs, bevor diese Bank wieder aufgelanden werden muss)
Nun , kommt
Und auch wieso bei 65536 * 8192 Collumns ~ nun REFI in sauberen 8192er Schritten skallieren muss. Integers halt
Ob man nun eine Bank vollfüllt bevor alles wieder neugeladen werden muss und man tRET (IC maximum charge retention time = 64ms)
Oder 2 Banks vollfüllt , dadurch zwar timing Zugriff limitiert, jedoch mehr Zeit vergehen darf bevor unsaubere Timings überlappen und eine halt-condition erstellen.
Alles reine Mathematik und Logik
Danke dass du gefragt hast.
TL;DR
RFC steps of 32 (DDR4 steps of 16)
RFCsb/pb steps of 16 or 24. I personally use 32 but thats my shenanigans;
Wie lange das PCB & IC design braucht und wie schnell es Charge verliert
Dass ist Pro IC SKU ein Unikat
somit werden pragmatische ns Richtwerte vorgegeben welche als JEDEC Grundspec darstehen;"Hat X lange zu brauchen ansonnsten Design-Fail, Hat tDelta zu halten ansonnsten Design-Fail ~ usw und so fort"
Richtwerte, keine Fakten
Faktuell nur gegengeprüft, jedoch weiterhin weit weg von den Limits. RAM arbeitet einfach nicht auf worldclock !
Beitrag automatisch zusammengeführt:
EDIT 2:
Hynix A ~ etwa 120-130ns im FGR modus (standart)
HynixM ~ 16gb etwa 150-155ns, 24gb etwa 160-170ns
RFCpb ungefähr 30-32ns unter RFCab. Minimum um die 95ns, anliegend nahe 105-110ns.
Aber das ASUS Bios Team macht es schon sehr gut auf Auto.
Lass dir nicht einreden dass 140 anstelle 120ns "eine Schande" sind. Oder high 170 anstelle ~150 für 24gb.
RFC besonders im FinegranularityModus ist nicht soo wichtig.
Dafür sind die ICs selber doppelt bzw dreifach so groß wie man sie aus DDR4 Zeiten kennt // bald sind die 4GB Samsungs kaufbar
Genug Banks um das generell schon abzufangen. Das selbe mit den tRRD_ delays bzw tRAS;
Ich arbeite noch an Intels RFCpb, sowie AMDs RFCsb // beides abseits der Specs
Steps of 24 oder steps of 32 passt, soweit renne ich sie immer auf steps of 32
Viele Nutzer auf Steps of 24 oder 16. Je nachdem.
Usw
Gegenprüfen nicht vergessen, ob der Schritt überhaupt realistisch rennbar ist.
Wenn du RFC mini meinst, gibt es soweit zu wenige DDR5 Dokumente welche Chargeloss auf Zeit dokumentieren.
Ebenso wir tRC nicht mehr benützt usw. DDR5 ist komplett anders zu DDR4;
Es steht aber eigentlich dabei als disclaimer.
tRC selbst ausgerechnet kommt sogar noch hin bis 6* , wenn man RAS als RCD+RTP bedenkt und "row needed closure" erwartet.
Aber das ist mir alles zu ungenau. Es refresht anders, komplett anders zu DDR4 consumer.
Ohne eine gescheite Thermal/Discharge Liste komme ich nirgendwo weiter oder 10x die selben memICs auf unterschiedlichen DIMM-PCBs zu besitzen;
Womöglich gibt es bei HBM2/2e etwas abschaubares, wie sonnst auch immer auf GDDR5/X.
Aber nein, soweit einfach nicht möglich. Nichts für DDR5 außer logische Specifications;
Ich müsste einen Tipp zu REFI & tRET Thema erhalten und endlich Nvidia's interleaving Trick mit "row buffer locality" begreifen. // und auch Zeit + Resourcen finden weiterzuforschen.
Dann eventuel lässt es sich besser damit arbeiten. Soweit nichts;
Ansonnsten welche Formel ?
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Evtl noch ein Geheimtipp:
en.colorful.cn
Gibt's für knapp unter 200€ in der Türkei.
Colorful-Product-BATTLE-AX Z790AK-PLUS D5 V20
Established in 1995, Colorful is a brand with 20+ year history. Colorful business range covers DIY product lines, including graphics card, motherboard, RAM, SSD, all-in-one PC, server, etc. It is a comprehensive company that holds the largest share in the Chinese graphics card market...
en.colorful.cn
tRFC mini DDR4/DDR5 WIP
Ich verstehe nur Bahnhof, aber trotzdem erstmal Danke. Habe mich gestern etwas falsch Ausgedrückt. Meinte den tRFC Calculator, die Werte dort habe ich für mein 8000 Setup übernommen.
Was kann da noch Optimiert werden oder ist falsch eingestellt, zwecks Stabilität.? > Beitrag https://www.hardwareluxx.de/community/threads/intel-ddr5-ram-oc-thread.1306827/post-30352808
tWTR_S 7
tWTR_L 24
// tRDWR__SG/DG auto, damit du dich mit tCWL Formeln nicht rumschlagen musst
Sobald TM5 stabil, tWTR_S 4
TM5 errors immer screenshotten (3-4 sammeln)
Falls instabil vorerst tRDWR_SG/DG hoch, für IMC efficiency
RFC:
600 RFCpb
Könnte auf selber Spannung RCD 49 & RAS 65 brauchen.
Falls Class-V M-Die , könnte RTP 15 & dann RAS nochmals +3 ~ brauchen.
600 RFCpb
Könnte auf selber Spannung RCD 49 & RAS 65 brauchen.
Falls Class-V M-Die , könnte RTP 15 & dann RAS nochmals +3 ~ brauchen.
Beitrag automatisch zusammengeführt:
Schöne RCD
Solltest du dir mal überlegen die BoltV's zu öffnen, wäre es Nett zu wissen ob alle schon Class V sind, oder es ausnahmen gibt
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tRFC mini DDR4/DDR5 WIP
docs.google.com
Ich verstehe nur Bahnhof, aber trotzdem erstmal Danke. Habe mich gestern etwas falsch Ausgedrückt. Meinte den tRFC Calculator, die Werte dort habe ich für mein 8000 Setup übernommen.
Was kann da noch Optimiert werden oder ist falsch eingestellt, zwecks Stabilität.? > Beitrag https://www.hardwareluxx.de/community/threads/intel-ddr5-ram-oc-thread.1306827/post-30352808
tRFC verhält sich etwa so wie tCL oder tRCD. Wenn zu scharf eingestellt, siehst Du umgehend Fehler oder es bootet garnicht erst. Daher ist es sehr einfach zu optimieren... einfach runter drehen bis es nicht mehr läuft und im Zweifel 5-10% zurück. Das ist dann auch stabil, da gibts nichts weiter zu optimieren.
Resliche timings siehe die Unzähligen screenshots hier.
the_patchelor
Legende
ich komme bei den googlesheet nicht ganz mit, was ist mein tRFC2 Wert und was oder wie leite ich den tRFCpb ab?
im Calculator hab ich 8 Werte, irgendwie für tRFC (die für 3Gb M-Dies noch per tRFC ns Wert angepasst werden müssen oder?)
Hatte testweise 170/140ns glaube ich eingestellt.
2x24GB 8400 C40-52-52-79
mit den Fehlercodes aus TM5 so nach und nach zusammengestückelt.
nach 10-12 Minuten kommen dann 10er, Luftgekühlt halt...
im Calculator hab ich 8 Werte, irgendwie für tRFC (die für 3Gb M-Dies noch per tRFC ns Wert angepasst werden müssen oder?)
Hatte testweise 170/140ns glaube ich eingestellt.
2x24GB 8400 C40-52-52-79
mit den Fehlercodes aus TM5 so nach und nach zusammengestückelt.
nach 10-12 Minuten kommen dann 10er, Luftgekühlt halt...
Zuletzt bearbeitet:
Mal wieder was vom Bastelrechner mit 7800MT/s:
Board: Colorful CVT B760i D5
CPU: 13900K
Ram: G.Skill Trident Z5 F5-7200J3646F24GX2-TZ5RK
SA 1,16V
VDDQ 1,36V
VDD2 1,38V
VDD/VDDQ 1,45V
Die 8000 wollen noch nicht ganz fehlerfrei laufen, mal schauen ob ich das noch schaffe vor dem Wechsel aufs Tachyon. Dann werden auch die Timings nachgeschärft.
Board: Colorful CVT B760i D5
CPU: 13900K
Ram: G.Skill Trident Z5 F5-7200J3646F24GX2-TZ5RK
SA 1,16V
VDDQ 1,36V
VDD2 1,38V
VDD/VDDQ 1,45V
Die 8000 wollen noch nicht ganz fehlerfrei laufen, mal schauen ob ich das noch schaffe vor dem Wechsel aufs Tachyon. Dann werden auch die Timings nachgeschärft.
Liegt noch verpackt im Keller
Trau dich!Liegt noch verpackt im Keller