3900X has 2 interconnects (1 per chiplet) leading to the I/O die. But what we were not told, is that those 2 interconnects are merged into a single interconnect, also running at 32 bytes/cycle at 1800 MHz that connects the data fabric in the I/O Die to the Memory Controller circuitry.
That single interconnect to the memory limits Ryzen CPUs to a total 56.7GB/s between CPU Cores and the dual Channel RAM that in itself also has a theoretical Max bandwidth that matches the Infinity Fabric up to 1800 MHz.
Above that frequency, the Infinity Fabric will start to bottleneck the Installed 4000+MT/s RAM. (That aspect of Zen is in common with Zen 1 and 1+)
That 56.7GB/s of total end to end bandwidth also has to be shared with the GPU and its DMA memory access requirements.
A 2080ti running at full speed is demanding upwards of 15GB/s of data, that, while separated directly from the hardware by the kernel virtual memory management, ultimately has to come from the L3 Cache or the RAM over those physical interconnects.
That requires the CPU cores to sacrifice memory bandwidth and leads to longer CPU stalls as the cores have to wait idle for memory requests due to the reduction in available bandwidth for the CPU.
Conversely, Intel Ringbus ties L3 cache speed to the Ring topology interconnect and also transfers data at 32 bytes/cycle yet, with a Cache multiplier of x42, it gives the transport, that also has to share the bandwidth between CPU and GPU memory needs, a total theoretical bandwidth of 144GB/s providing a surplus of bandwidth that is shared between CPU and GPU to access memory.
