Here we can get a good look at what we consider the most significant change to the standard ASUS BIOS offering in years. "Common Performance Level", more correctly known as MCH Read Delay (tRD), allows the user to specifically establish a desired value, something that was not entirely possible in the past. Earlier versions of "Ai Transaction Booster" only allowed the user to apply an offset, which made controlling tRD difficult when the base value was unknown.
Additionally, each FSB bus cycle "phase" for each channel can be further manipulated. "CHA" and "CHB" refer to the two independent memory channels in a dual-channel memory configuration. Installing only one memory DIMM, or certain combinations of mismatched memory module pairings across all four expansion slots, results in the motherboard defaulting to single-channel operation; otherwise there are two memory channels in operation, which enhances overall system performance. The number of phases per channel depends on the memory divider in use (each channel will always have the same number of channels though) - a 3:2 memory divider has two phases, 4:3 has three, and 8:5 has five, for example. We will explore the theory behind this truth shortly.
Setting a single channel/phase "Pull-In" to enabled has the effect of lowering that particular phase's associated tRD value to one below the Common Performance Level (the "base" tRD). Leaving the setting disabled leaves the phase unadjusted, in which case it is the same as the base tRD. Much like memory timings, lower tRD values bring greater performance. As we will see, these settings primarily allow users to squeeze out any unclaimed performance benefit possible with the current tRD when the next "lower" Common Performance Level is unachievable. Do not feel as though you need to understand what all of this means right now, as we will cover all of this and much more in excruciating detail soon enough.
