tibcsi0407
Semiprofi
Thank you!Can you give on this a scroll capture, phone or merging two screenshots
Of the listed (target) DieSense (VID) for every 100MHz step ?
The written out values, just to be sure
We target near 1150mV CoreVID or 1160ish Vout.
Around 1180 for VT3.
We hit atm 1230 Vout
But it's not just "lower one point"
if you lower one point or transitions are bad, it will crash.
Target is to lower min and mid points, to smooth peak ~ soo overall whole curve drops.
LL(C) Telemetry faking is a linear drop. Substrate has not linear voltage scaling.
I need you later to check bootable high voltage.
To make sure you have same very-leaky but XOC SA/MC stable chip.
Nonleaky are very different than those 1.46+ ones.
Some are high leakage some are just "failed" bad bins.
Some need high voltage curve due to thermal target, some 14700K rebrands need more voltage or fail target clock
There are many variables why it is how it is.
Important is that ICCMAX is not hit, for any of those harsh loads.
PL4 itself will bother for memOC. It's not just the cores~
// But it has to exist for health, safety and for jitter/transient loadchange spikes
We can fake and bypass, but if we start putting bandaid on bandaid like PLL usage - this leads to nowhere
So we can lower the Vcore keepi SFT stable?
Here are the points with the suggested offsets:
My E-cores are very weak and they are at 45X right now, but I can reduce them if needed.
The bitrate is not reduced, just checked it with 2 minutes rounds and it's okay. Vst is 1.26 x 10^10 Vt3 is 1.45 x 10^10