tibcsi0407
Semiprofi
But they are still slower by a lot.
Hope someone will release some good DDR5 IC too, but seems like only Hynix interested in this one.
[Sammelthread] Intel DDR5 RAM OC Thread
- Ersteller even.de
- Erstellt am
Hope someone will release some good DDR5 IC too, but seems like only Hynix interested in this one.
It is JEDEC 5600
And JEDEC is binning at 1.1v
Why they are stock at 1.35v is strange
But 5600C36-38 sounds reasonable vs Hynix 5600C46-45-45
Soo if they don't practice marketing shenanigans, this could get interesting.
Technically they wouldn't need to.
Beitrag automatisch zusammengeführt:
Ya ?
I dont see anybody working with JEDEC 5600 Micron's.
Like any at all.
tibcsi0407
Semiprofi
mm mmSaw this only:
*Official* Intel DDR5 OC and 24/7 daily Memory Stability...
www.overclock.net
definitely not 5600 JEDEC nor 36-38-38's
4800 40-40 kits.
Maybe ask him for a https://www.passmark.com/products/rammon/
I mean,
8800 CAS 72 does sound a bit awkward, but 14ns RCD are
Micron 8800C58-62-62-140 sounds realistic @ idk what that rating is ~ 1.1v ??
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tibcsi0407
Semiprofi
It's an older post, saw different kit's from him since then.
Didn't Igor review the new Micron kits last year?
Maybe missed,
i saw the cheap Pro lineup just recently as 5600 kits.
They definitely are capable, if they want.
EDIT:
Yes
vs 5600 36-38-38 @ idk what voltage
Different ICs and smaller CAS/RCD delta.
EDIT2:
Its even worse
4800 C41-41 @ 1.1v JEDEC.
Other was 1.2v XMP, not JEDEC.
Beitrag automatisch zusammengeführt:
@tibcsi0407
Those were my Viper Hynix-M early on
Hynix 6000 30-36 @ 1.3(5)v ~ (XMP 6000C36-36 @ 1.25v)
vs XMP
Micron 6000 36-38 @ 1.35v
If they are just 1-2 ticks worse, it sounds good
But i don't know. I was big amateur back then~
Were not new.
Current listed is not out yet.
Whatever 16gb pro OC lineup is supposed to be.
Other Pro lineup are brand new too
Soo they do play with marketing a bit
JEDEC 5600 rating is 46-45 @ 1.1v .
They dont sell slower kits because ICs are 5600 rated not 4800. 5600 & 6000 kits only.
Then 36-38 is 1.35v rated. How they can call it JEDEC 36-38 is beyond me.
But with math, it still sounds ok actually. I'd like to try them. Whatever new they will release as 16gb option.
EDIT2:
So its that @ 1.1v.
I guess they can do better as 5600 40-40 kits vs 46-45 @ 1.1v
But ya~
Curious
Hynix-A
Definitely lower tier at low voltage.
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Rules are Dynamic.
Up to self adjusting V/R-odt of sample.
Self adjusting because up to leakage factor of sample.
High VID = leaky, Low VID = non leaky.
Leaky = 1.48++
Non Leaky= 1.38-1.42v
High SA , lower IVR VDDQ ⟺ Mem VDDQ Delta ~ because weak ODT
Low SA, big VDDQ Delta, because strong ODT.
VDD2 = ODT defined and sample leakage defined.
Rules adapt to CPU
VDDQ ⟺ VDDQ changes by capacity, Boardlayout , Board ODT/RTT Tuning & Rodt state defined by sample and SA state.
When SA bug happens, depends on sample leakage factor.
Freeze on TM5 are ODT issues inside CPU. Non mem related
#0 are dropped links between CPU & MEM.
#6 is mem primaries or CPU IMC.
#8 CPU synchronization issue for writes. Writes are handled by the CPU.
Working Order:
Know V/F Curve ~ to decide on VDD(2)_CPU
Decide whatever SA.
VDDQ Training off.
Sample Max VDDQ⟺VDDQ delta and min delta till y-cruncher 90min+TM5 1usmus 25c.
Of both borders use 80-85% of median.
If 60 & 120 , use 90-105mV (steps 15mV).
If 75 & 150, use ~120-135mV
And so on.
Higher capacity , smaller delta.
2DPC, vs 1DPC ~ smaller delta.
Weaker Boarddesign ~ smaller delta.
Best "rules" i can give you.
Too much "it depends".
InMem Delta rules:
Step 30mV.
60mV delta works always
105mV delta is a powering/rtt check
240mV delta about user max ~ seen functional but never on stock RTTs.
300mV delta is PMIC max.
VDDQ⟺VDDQ is crucial
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My CPU samples show the exact oposite.
Btw., why is high VID = high leakage? Isn't it the other way around? Leaky = more power draw but faster switching = lower VID, or not?
The opposite.
SA is just SA.
ODT changes
High ODT impedance value ~ weaker signal
Low ODT impedance value ~ stronger signal.
SA changing ODT is a side-influence.
ODT adapts dynamically.
If we check on voltage required to even leakage factor:
Leaky samples are hungry for more voltage but scale better with more amperage
Non leaky samples scale better with lower voltage, but may or may not dislike high amperage.
If voltage level is the same:
Then leaky samples may reach higher clock vs non leaky samples
if amperage/powerdraw level is the same:
Then leaky samples will need less voltage to reach high powerdraw
vs non leaky samples.
If we even out same clock:
leaky sample will have it harder & require more voltage vs non leaky samples.
If we even out -200°c thermals and so internal resistance:
Leaky samples will scale better vs non leaky samples.
All a perspective thing.
Same story with ASIC % which equals LkgID (leakage factor)
EDIT:
Basically leaky samples only are useful at lower thermals, till SignalIntegrity becomes unbearable @ target high voltage.
Non leaky samples require less voltage which means better SI and easier to use stronger amplification of set low voltage (stronger/lower ODT).
Hope that explains~
H24M is either 5600 (MGBD) or 6400 (MHBD). Whereas the MGBDs usually clock better despite being JEDEC 5600.That may be the good thing
8*3GB IC are JEDEC 5600 vs 4800 on Hynix
But what is 16gb "pro overclocking"
Yes MHBD is newer.
But there can be a powering issue on newer ICs.
RTTs are different too.
Unless specification scale up "degraded" with 6400 JEDEC
// (if they are even, given SK Hynix started to push 24gb-M & 16gb-A under 4800MT/s Class V spec ... which absolutely is not JEDEC-5600 spec, let alone 6400 dreams. Its just marketing JEDEC-5600 target, if even.)
Then there is no reason why higher JEDEC should clock worse.
Only if specification targets degraded due to failure in meeting target. Then for sure it makes sense.
Correct practice is like example above. Slower timings @ equal or better ns worldclock. Rising onwards by MT/s.
For Micron that is till 8000 @ 1.1v JEDEC. (14ns CAS)
SK-Hynix keeps their datasheets private soo one can not point to that part.
But if they failed target & time was of pressure, then that's about how you go ~ you degrade specs or twist specifications and words.
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That’s only in theory:
光威神策用了mhbd - 电脑讨论(新) - Chiphell - 分享与交流用户体验
光威神策用了mhbd,自己到手掰了一下看231030批次芝奇十铨半年前就用上了，小参不如adie，国产现在跟进一下ahbd才是重头戏 ...,电脑讨论(新),讨论区-生活与技术的讨论 ,Chiphell - 分享与交流用户体验
www.chiphell.com
And here is the logic error, or not
Leaky = same clock at lower voltage or higher clock at same voltage = lower VID
Yess that part/sku number is missleadingThat’s only in theory:
光威神策用了mhbd - 电脑讨论(新) - Chiphell - 分享与交流用户体验
光威神策用了mhbd,自己到手掰了一下看231030批次芝奇十铨半年前就用上了，小参不如adie，国产现在跟进一下ahbd才是重头戏 ...,电脑讨论(新),讨论区-生活与技术的讨论 ,Chiphell - 分享与交流用户体验
Not only do they themselves break it by sepperating to Class V vs Class-A
but also don't rate current kits correctly.
Everything i've seen that doesnt come straight out of them, is JEDEC4800 testet.
Probably soo higher margins pass through & yield is higher.
Add ontop that supposedly higher "visually rated" kits perform worse.
I don't know what to think more.
Its kind of obvious, even if you add 4 ratings (2 more ratings for non 3DS) , you still don't follow them.
It is embarrassing but i don't know what to say. Also it's bad practice to bad-pr complain.
Yet, like "why do you even call your kits JEDEC-5600 qualified ... if you don't even test at that speed."
Yea no,
If one has nothing good to say, they should better say nothing.
Give them time
It may be target as JEDEC-6400, but i absolutely struggle to believe its actually meeting that target 🤭
Beitrag automatisch zusammengeführt:
Voltage neither means amperage nor clockAnd here is the logic error, or not
Leaky = same clock at lower voltage or higher clock at same voltage = lower VID
The "higher clock at same voltage target" has thermal as variable
The "same clock target at lower voltage" has efficiency as variable
The Stilt on OCN like 8? years ago, explained it well.
ASIC quality replaced with "leakage-factor in %".
For old days it was high ASIC = non leaky sample
But for AMD and current target its "leakage factor in %"
How much does it leak, where lower % is better.
Thermal variable
Impedance variable
Resistance variable
Voltage & clock are irrelevant~
Amperage is an end product
Thermals & leakage factor/picosec(time) go hand-in-hand.
^ but thermal & substrate foldover point was mostly solved last ~4 years.
// It was an issue with Skylake (2015) where substrate foldover point was ~72°C.
// Now both companies AMD/Intel test at 130-135°C their substrate with ~6 months time limit. 95-105° are common temperatures since 2015.
// Its not a problem anymore and doesnt influence too much leakage factor. Cold on the other hand changes resistance and material properties. This includes the copper-mainboard, even if crystal is quite stable.
// High temps topic is long time resolved. For most ICs too. Only Cube (3D) stacked memory/cache [transistors] still needs bit more time to mature. As thermals still mess a lot with our capacitor's style.
// GaN has quite interesting properties.
Beitrag automatisch zusammengeführt:
Maybe it can be found with wayback archieves
AMD Cards and ASIC Quality
www.overclock.net
Generally The Stilt was very educational and supportive in the early days. There is much to learn, if you can still find his posts.
Also very polite, to say the least~~
Elmor & Shamino can be put in the same bag.
Although didn't have a chance to catch much education from both sadly. I joined too late in our field.
Beitrag automatisch zusammengeführt:
@X909
Basically
More efficient sample, will come with lower VIDs.
But more efficient sample does not guarantee higher clock scaling.
It just guarantee's lower leakage till some point
It also does not guarantee less SI affectness.
It only guarantee's better SNR/SI till some clock/strain point.
Now strainpoint of thermals can be excluded for crystal.
Substrate foldover point has been moved to the 115-120°C point. GPUs included.
// Up to manufacturing node i guess. Low nm nodes with high efficiency tend to have low thermal foldover points.
But ~ voltage sustain duration (leakage) vs voltage transmission (resistance) are two different things.
An efficient sample doesnt mean it has lower resistance vs a leaky sample
But a leaky sample may... have it easier with higher voltage, due to it being shaped as such sample.
// And still that higher voltage, doesn't always have to mean more powerdraw. That depends on thermal condition and internal resistance factor.
If it wasnt shaped as such sample, it would never meet clock target and be rated at lower voltage ~ "looking" like an efficient sample
But only looking like, till you approach its limits.
Now if you scale that clock up, what is efficient and what is not ... well that changes
perspective changes.// Hence also voltage req between frequency points changes. Efficiency changes, its not linear.
Soo all leakage factors have their corresponding range and conditions~
Thermal conditions we matured well last, actually its 8-9 years already.
Clock conditions we skyrocketed +1000-1500MHz last 3 years. Around there.
But if we match clock targets
Then an efficient sample will need less voltage and may or may not produce less powerdraw
If it does is another variable, how it works with the voltage you give it. Internal resistance is silicon lottery a bit.
But if rating is correct and it needs less voltage for same target clock ~ then noise will be better too, due to simply needing less voltage
Just within its range, till it also becomes a leaky sample or worse. Usually foldover point drops like a stone. Effect should be very visible on memtransistors.
I hope this time it makes a bit more sense~~
Please let me know , if it still doesnt.
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tibcsi0407
Semiprofi
Hm, could be interesting. BIOS support is questionable.Maybe missed,
i saw the cheap Pro lineup just recently as 5600 kits.
They definitely are capable, if they want.
EDIT:
Anhang anzeigen 973850
YesJEDECXMP 4800 C28-36-36 [Igorslab] & 5600 32-42-42 @ 1.2v
vs 5600 36-38-38 @ idk what voltage
Different ICs and smaller CAS/RCD delta.
EDIT2:
Its even worse
Anhang anzeigen 973851
4800 C41-41 @ 1.1v JEDEC.
Other was 1.2v XMP, not JEDEC.
Beitrag automatisch zusammengeführt:
@tibcsi0407
Those were my Viper Hynix-M early on
Anhang anzeigen 973855
Hynix 6000 30-36 @ 1.3(5)v ~ (XMP 6000C36-36 @ 1.25v)
vs XMP
Micron 6000 36-38 @ 1.35v
If they are just 1-2 ticks worse, it sounds good
But i don't know. I was big amateur back then~
Were not new.
Current listed is not out yet.
Whatever 16gb pro OC lineup is supposed to be.
Other Pro lineup are brand new too
Anhang anzeigen 973861
Soo they do play with marketing a bit
JEDEC 5600 rating is 46-45 @ 1.1v .
They dont sell slower kits because ICs are 5600 rated not 4800. 5600 & 6000 kits only.
Then 36-38 is 1.35v rated. How they can call it JEDEC 36-38 is beyond me.
But with math, it still sounds ok actually. I'd like to try them. Whatever new they will release as 16gb option.
EDIT2:
Anhang anzeigen 973863
So its that @ 1.1v.
I guess they can do better as 5600 40-40 kits vs 46-45 @ 1.1v
But ya~
Curious
Hynix-A
Anhang anzeigen 973865
Definitely lower tier at low voltage.
@tibcsi0407 so i swapped to the 1001 bios today and so far i just needed to change my offsets slightly otherwise memory worked fine with same settings from 0080 which is weird cuz 0904 for me was unstable in memory and cpu but 1001 is fine, but you also had a problem with this 1 lol stuff is so confusing i wish they would just flat out specifically list off the changes instead of some generic term " improved system performance " and im sure there is reasons they don't but damn is it annoying lol
Good...eh Timezone i guess 🤭🥱
I think "added 256GB support"
Are Samsungs brand new 4gb IC. (4x64GB dimms)
Thinking about it, other IC Manufactures arent ready with it yet.
Unless Team knowns more than me, i dont think we can run 2Heigh 2GB ICs
As 48gb per side UDIMM
That would be actual DualRank, 96GB dimms.
But i dont think UDIMM can physically do that.
Else we wouldnt waste time with (virtual) logical-dual rank. That has zero properties of actual dual rank.
// Although consumer IMC may? has support for RDIMM. Like it has for LPDDR4/5.
// If somebody would make a server class Board to have fun with RDIMM on an OCing CPU. Topic (AI) dataset-processing.
Soo must be brand-new's Samsung IC compatiblity & RTTs for 2DPC
Whyever changelog is put on 1 DPC apex Boards.
Guess just global firmware branch (changelog) practices.
I think "added 256GB support"
Are Samsungs brand new 4gb IC. (4x64GB dimms)
Thinking about it, other IC Manufactures arent ready with it yet.
Unless Team knowns more than me, i dont think we can run 2Heigh 2GB ICs
As 48gb per side UDIMM
That would be actual DualRank, 96GB dimms.
But i dont think UDIMM can physically do that.
Else we wouldnt waste time with (virtual) logical-dual rank. That has zero properties of actual dual rank.
// Although consumer IMC may? has support for RDIMM. Like it has for LPDDR4/5.
// If somebody would make a server class Board to have fun with RDIMM on an OCing CPU. Topic (AI) dataset-processing.
Soo must be brand-new's Samsung IC compatiblity & RTTs for 2DPC
Whyever changelog is put on 1 DPC apex Boards.
Guess just global firmware branch (changelog) practices.
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Hi @Veii, how are you? I liked all your posts here!Rules are dynamic .
Up to self-adjusting V/R - odt of sample .
Self-adjusting because up to leakage factor of sample.
High VID = leaky, Low VID = non-leaky.
Leaky = 1.48++
Non-leaky=1.38-1.42v
High SA , lower IVR VDDQ ⟺ Mem VDDQ Delta ~ because weak ODT
Low SA, big VDDQ Delta, because strong ODT.
VDD2 = ODT defined and sample leakage defined.
Rules adapt to CPU
VDDQ ⟺ VDDQ changes by capacity, board layout, board ODT/RTT tuning & Rodt state defined by sample and SA state.
When SA bug happens, depends on sample leakage factor.
Freeze on TM5 are ODT issues inside CPU. Not meme related
#0 are dropped links between CPU & MEM.
#6 is mem primaries or CPU IMC.
#8 CPU synchronization issue for writes. Writes are handled by the CPU.
Working order :
Know V/F Curve ~ to decide on VDD(2)_CPU
Decide whatever SA.
VDDQ training off.
Sample Max VDDQ⟺VDDQ delta and min delta till y-cruncher 90min+TM5 1usmus 25c.
Of both borders use 80-85% of median.
If 60 & 120 , use 90-105mV (steps 15mV).
If 75 & 150, use ~120-135mV
And so on.
Higher capacity, smaller delta.
2DPC, vs 1DPC ~ smaller delta.
Weaker board design ~ smaller delta.
Best “rules” I can give you.
Too much “it depends”.
InMem Delta rules :
Step 30mV.
60mV delta always works
105mV delta is a powering/rtt check
240mV delta about user max ~ seen functional but never on stock RTTs.
300mV delta is PMIC max.
VDDQ⟺VDDQ is crucial
(I have a library of OCN bookmarks of your posts, many from AMD) I'm still working with the voltages, maybe you can help me with some advice since there are some points that I don't quite understand yet.My mem kit is a Gskill 8000 2x16 A-Die at 1.45 XMP. (similar to the 7800 2x16 at 1.4v). Would my XMP value be the floor of VDDQ_mem? Or for example with a RON of 48/40-40-48, could VDDQ_mem go down?
I'm trying with the following values:
8200/8266 loose timings (38-49-49-49-65)
VDDQ_mem 1.45
VDD_mem 1.51 (following the 60mV rule)
VDDQCPU-TX+ 1.23v it seems that the lower the better (it would be an objective delta, right?)
MC 1.48v (I didn't understand when you said that Know V/F Curve ~ to decide on VDD(2)_CPU). How can the MC value be interpreted on the V/F?
SA 1.18, I notice that the lower it is, the faster YC VST-VT3 works. The higher the SA, the slower the execution of VST-VT3. considering the detail I have between VDDQ and TX.
Regarding my 14900k CPU, I understand that it is non-leaky, my V/F is on the edge, at 1423 maximum. I'm working on it with the help of
@tibcsi0407, he did an impressive work!! Thanks @tibcsi0407! 🙌
Another point, I realized that a Pcore, 7, shoots up in temperature. It is always the same as in the transitions from VST to VT3 (mostly in VT3), having a current peak, it fails. Can a single core be limited with an offset? I know it's pretty basic, but I don't know if it's better to touch the entire V/F or add an offset to a Core. Before, this error did not appear because I always had a limit, either PL1/2 or an AVX -2/-4. and with that I was at 253/280. Now without limits, I can reach ~310W but I notice that all the processors have relatively good temperatures except one.
Thank you very much as always!
Beitrag automatisch zusammengeführt:
Hi @tibcsi0407, how are you? I just realized I just realized that you are from Hungary, you know that my parents are from Hungary, in fact I am a Hungarian citizen but I was born in Argentina, and believe it or not, I still have not known the land of my parents. It's something I'm going to do this year!, Regarding the AC_LL, then if, for example, I define 0.6, do the values that I defined in the V/F that I shared with you in my previous post move to the right? I say, because one of the errors that I think I have is that P3 is very low from the factory, so I have to give it +35/40mv to keep it horizontal, but then to achieve the double S, I increase the voltage of P4 and P5 , and then eating with an undervolt for the rest of the curve, which I think is what causes CB23 to fail and everything in general. If so, maybe those values could work, but they are high jumps compared to my original curve, what do you think?
Thanks!
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tibcsi0407
Semiprofi
What's your current mem speed? Some of us experienced issues above 8400 with the new release.
I am sure it has to work, but I need to find the key for that, which is not easy.
Hi @tibcsi0407,I just tried AC at 0.6 and the curve looked much better, I just corrected P3 so that it doesn't go down, and eating at 719 instead of 711, I think it looks much better, even without achieving the double S shape
It seems much better, doesn't it? Thanks
tibcsi0407
Semiprofi
Hi,Hi @Veii, how are you? I liked all your posts here!
My mem kit is a Gskill 8000 2x16 A-Die at 1.45 XMP. (similar to the 7800 2x16 at 1.4v). Would my XMP value be the floor of VDDQ_mem? Or for example with a RON of 48/40-40-48, could VDDQ_mem go down?
I'm trying with the following values:
8200/8266 loose timings (38-49-49-49-65)
VDDQ_mem 1.45
VDD_mem 1.51 (following the 60mV rule)
VDDQCPU-TX+ 1.23v it seems that the lower the better (it would be an objective delta, right?)
MC 1.48v (I didn't understand when you said that Know V/F Curve ~ to decide on VDD(2)_CPU). How can the MC value be interpreted on the V/F?
SA 1.18, I notice that the lower it is, the faster YC VST-VT3 works. The higher the SA, the slower the execution of VST-VT3. considering the detail I have between VDDQ and TX.
Regarding my 14900k CPU, I understand that it is non-leaky, my V/F is on the edge, at 1423 maximum. I'm working on it with the help of
@tibcsi0407, he did an impressive work!! Thanks @tibcsi0407! 🙌
I didn't understand when you say "of both borders use 80-85% of median", If 60 & 120 , use 90-105mV (steps 15mV). If 75 & 150, use ~120-135mV. I don't understand what you mean by the "borders", it went directly to a target of max 230mv for the 16GB kits. Before, I left TX in Auto which gave me a fixed value of 1.35, just 100mV of delta. I'd like to understand this concept so I can build my funtation well. Thanks
Another point, I realized that a Pcore, 7, shoots up in temperature. It is always the same as in the transitions from VST to VT3 (mostly in VT3), having a current peak, it fails. Can a single core be limited with an offset? I know it's pretty basic, but I don't know if it's better to touch the entire V/F or add an offset to a Core. Before, this error did not appear because I always had a limit, either PL1/2 or an AVX -2/-4. and with that I was at 253/280. Now without limits, I can reach ~310W but I notice that all the processors have relatively good temperatures except one.
You taught me a while ago how to define RTTs, in fact before with my previous 13700k CPU, I always used them flat, the adapted version of Shamito, 40-34-34-34/240-0-0/60(80) - 40-40, now I'll leave you by car. And for 8200/8266, 172 / 90 in CTL0 DQVrefup/down. For now I only have the RONs and CTL0 DQVref set, RTTs in Auto. Is it okay for me to start leaving RTT on Auto for now?
Thank you very much as always!
Beitrag automatisch zusammengeführt:
Hi @tibcsi0407, how are you? I just realized I just realized that you are from Hungary, you know that my parents are from Hungary, in fact I am a Hungarian citizen but I was born in Argentina, and believe it or not, I still have not known the land of my parents. It's something I'm going to do this year!, Regarding the AC_LL, then if, for example, I define 0.6, do the values that I defined in the V/F that I shared with you in my previous post move to the right? I say, because one of the errors that I think I have is that P3 is very low from the factory, so I have to give it +35/40mv to keep it horizontal, but then to achieve the double S, I increase the voltage of P4 and P5 , and then eating with an undervolt for the rest of the curve, which I think is what causes CB23 to fail and everything in general. If so, maybe those values could work, but they are high jumps compared to my original curve, what do you think?
Oh, my SVID Behavior is Trained, and my MCE set to Enable Remove All limits. If I set ASUS MultiCore Enhancement [Auto – Lets BIOS Optimize], it set PL1 to 253W. I don't understand why it doesn't do it to you, but every time I select that, PL1 option it goes to 253. Even if I disable the TVB Voltage optimizations like you have. The only way to not limit anything is by setting MCE to "Enable Remove all limits"
Thanks!
Yes,I noticed first time your account name on OCN. The world is small. ☺️
I like the news shape better. Did you check the stability?
I believe MCE sets the option based on your cooling performance.
Beitrag automatisch zusammengeführt:
Looks cool.aybe you can raise the 51X point a little and you will get the shape. How is the performance?
I see.
mmmmHi @Veii! I'm also so so, but still pushing. Long story short, there was once a very happy OCN member with a good setup for his 13700k and 7200 with a Hero
I am not sure for how long this will remain the case with SA/IVR VDDQ.This configuration at 8000 was not stable, and I passed a little YC (maybe that's the error) and then TM5, then Karhu 9hs... and cold boot... I went to 8266 taking one of your recommendations from a previous post
What I did was, I lowered VDDQCPU to 1.22 and SA rised to 1.21 I realized that at 1.18 it failed quickly, perhaps TX at 1.22 is too low for VDDQ 1.45. I know SA can't get above TX, that's why they are so close.
Because SA is linear and a VID, while [IVR] VDD2 & VDDQ are not.
VIDs target , well target voltage while the other one is affected by ODT.
Hence lower values there may still be stronger. Its amperage matching.
No such thing on Vcore/ring/L$/VDDCR_SA.
It is ODT affected, but i dont think its the same way amplified.
IVR VDD/Q 1456-1220
SA 1220
MEM VDD/Q 1530-1455
Hmmm
That's 235 delta. @ 1220 SA.
And 80 in mem.
Mem probably is ok.
I guess play with VDDQ delta.
In 15mV steps till you fail boot. Then in 5mV steps up and down till it passes.
MVDDQ is not the fixed variable.
The delta between both is a fixed variable, that can change due to strain slightly.
It will change due to internal ODT for sure.
use the latest TM5What do you recommend me? I'm a little lost and frustrated...
Thanks like always!
Drop SA to 1.14v level and start with 7800MT/s.
Figure median of delta out. till TM5 gives a #0 or #6.
Keep VDD2 near 1.4v
Too extreme.
Most harsh loads are near 4.7-4.8GHz.
The ceiling needs to be rather curving downwards, else on TVB+ you spike too high
.
Die Berichte klingen nach einem überdruck Problem. Bzw eher ein krummer mount
Unterlegscheiben unter der Backplate erhöhen sogar den Druck davon.
Kannst du mir bitte den MC-SP 5x nacheinander auslesen lassen und mir die Werte davon durchgeben
Eins nach dem anderen.
CPU Write error.
WTR zu hoch.
WTRS immer 8 oder niedriger
WTRL meinstens doppelt RRDL mit ausnahmen.
tWR immer über WTRL mit ausnahmen.
#8 jedoch gehört der CPU. Meistens
CPU instabil. Wie erwähnt, bitte um ein remount bzw um ein 5*MC-SP check.
Federschrauben nur mit den fingerspitzen reindrehen.
Bzw anfangs gerne mit dem Schraubenzieher ansetzen und max andrehen, dann rausdrehen und alle 4 Schrauben mit den Fingerspitzen halten und reindrehen bis man nicht mehr kann.
Abseits dem, ja
Bei VDDQ Training off, wenn man das falsche VDDQ erwischt innerhalb 15mV steps ~ dann trainiert es garnicht.
Das ist gut so. Das soll so.
Wieso möchtest du die Timings abseits dem XMP ändern, es läuft ja
Der selbe Grund. Weniger Spannung = potentiell saubereres Signal.
Außerdem ist es nicht VDD_MEM welches Hitze erstellt.
VDD_MEM ist nur die Dataline.
Yes, and my first name is Laszlo, but here Martin is more "common", and yes, the world is small!
Well, the first thing I noticed is that I was able to run CB15 Extreme, but with AC at 0.6 the Core VID went up a lot when I ran all cores, that is, I'm limited by the temperature. I think I should do some undervolting in the curve and then raise AC a little, it would be a more efficient way to do an undervolt, right? I always read that to adjust AC we had to lower it as much as possible, which would be a mistake if the curve is not modified.
The only thing I don't understand is why one core, the P7, is rising in temperature compared to the rest, it is an important difference. That makes my tests crash when I go from VST to VT3. I hadn't noticed it, maybe because I always limited YC and had that false stability. I don't know why happens and how to fix it..
This is a 14th gen feature.
A new throttle system , up to 105° per core or 95° whole CPU.
Fused Curve is rated till that target.
tibcsi0407
Semiprofi
For me the top ratio, which is 62X on two cores works only like this. I tried negative offsets on top, but I got crashes in some apps. With a little + offet it works fine, but it's CPU and ratio dependent.
Slightly flatten higher, and pushed up with AC_LL doesnt want to work ?For me the top ratio, which is 62X on two cores works only like this. I tried negative offsets on top, but I got crashes in some apps. With a little + offet it works fine, but it's CPU and ratio dependent.
I see you spike too high. till 1.55vid
tibcsi0407
Semiprofi
That VID is funnily only the P0 core, but I have Core 4 and 5 set to get highest ratio.
I have no idea why it is doing this.
This is current daily hwinfo:
Look at the P0 VID.
You can also notice that that has the lowest VID too. Strange, I have no idea what is the reason for this.
The other thing you can notice, that VRM Power and Package power has a huge difference, but EC reading is always a meh
I bought a GEN14 Supercool block, it will have a little bit different pressure on the CPU, who knows, maybe it will help a little in mem OC too.
Anhänge
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Hi @Veii, thanks for your answer. I didn't know that it was a new feature of the 14th gen, in my graph it is more noticeable how the peak of the PCores occurs at a maximum of 89 and the P7 shoots up to 97. I'm limited by my cooling capacity to run YC and not even think in SFT where the Package Power is surely going to 330W. I have to make an undervolt using the curve, I was thinking if it is more convenient to achieve a more positive slope if, for example, I raise almost all the points by +10mV (except P3 which I must correct because it goes to the floor), and then with AC, which By default in LLC4 it is 0.269, could I try later to lower it to 0.2, is the rational ok? I mean, thinking that my CPU reaches 6GHz at 1.423V according to its factory V/F
This could be an option to what I mentioned above, does my approach seem good to you? Or should I do the opposite, undervolt the entire curve starting at P3 and then rise the AC_LL?
This could be an option to what I mentioned above, does my approach seem good to you? Or should I do the opposite, undervolt the entire curve starting at P3 and then rise the AC_LL?
Ok, I'm going to do that, could I start with 8000, which is the XMP Profile? Something you told me is that VDDQ and TX are a fixed variable, my question is if I should take as an initial value, for example, 1.45V (which is the XMP value for 8000 2x16 A-die) for a 1.25v TX? , or do I look for a lower value, for example 1.4V (mem) / 1.2 (tx) as borders? That is my great doubt!
I say because the Encore trains everything, badly, but it trains, I mean, it boots, and I have constant crashes in Windows (of course on a test partition), but all the BSOD Error 41 are for this, for trying to find the VDDQ Delta. Thanks for your help as always @Veii!!
tibcsi0407
Semiprofi
This could be due to the IHS. A delid / relid with TGC would help you a lot on your CPU temps.