tibcsi0407
Semiprofi
But they are still slower by a lot.8*3GB IC are JEDEC 5600 vs 4800 on Hynix
Hope someone will release some good DDR5 IC too, but seems like only Hynix interested in this one.
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But they are still slower by a lot.8*3GB IC are JEDEC 5600 vs 4800 on Hynix
Ya ?But they are still slower by a lot.
Saw this only:Ya ?
I dont see anybody working with JEDEC 5600 Micron's.
Like any at all.
mm mmSaw this only:
*Official* Intel DDR5 OC and 24/7 daily Memory Stability...
www.overclock.net
It's an older post, saw different kit's from him since then.mm mm
definitely not 5600 JEDEC nor 36-38-38's
4800 40-40 kits.
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Maybe ask him for a https://www.passmark.com/products/rammon/
Maybe missed,It's an older post, saw different kit's from him since then.
Didn't Igor review the new Micron kits last year?
Were not new.Didn't Igor review the new Micron kits last year?
@Veii welche Spannung steht in interaktion / Abhängigkeit zu VCCSA? Ist das VDDQ(TX) oder MC? Ich kann mir einfach nicht vorstellen, dass bei dem low VID chip die VCCSA höher sein muss als bei nem high VID chip.
Rules are Dynamic.Hi @Veii can you briefly tell me the basic voltage rules? Deltas and what voltages interact...
Rules are Dynamic.
Up to self adjusting R-odt of sample.
Self adjusting because up to leakage factor of sample.
High VID = leaky, Low VID = non leaky.
Leaky = 1.48++
Non Leaky= 1.38-1.42v
High SA , lower IVR VDDQ ⟺ Mem VDDQ Delta ~ because weak ODT
Low SA, big VDDQ Delta, because strong ODT.
The opposite.My CPU samples show the exact oposite.
Btw., why is high VID = high leakage? Isn't it the other way around? Leaky = more power draw but faster switching = lower VID, or not?
H24M is either 5600 (MGBD) or 6400 (MHBD). Whereas the MGBDs usually clock better despite being JEDEC 5600.That may be the good thing
8*3GB IC are JEDEC 5600 vs 4800 on Hynix
But what is 16gb "pro overclocking"
Yes MHBD is newer.H24M is either 5600 (MGBD) or 6400 (MHBD). Whereas the MGBDs usually clock better despite being JEDEC 5600.
Unless specification scale up "degraded" with 6400 JEDEC
// (if they are even, given SK Hynix started to push 24gb-M & 16gb-A under 4800MT/s Class V spec ... which absolutely is not JEDEC-5600 spec, let alone 6400 dreams)
Then there is no reason why higher JEDEC should clock worse.
If voltage level is the same:
Then leaky samples may reach higher clock vs non leaky samples
If we even out same clock:
leaky sample will have it harder & require more voltage vs non leaky samples.
Yess that part/sku number is missleadingThat’s only in theory:
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Voltage neither means amperage nor clockAnd here is the logic error, or not
Leaky = same clock at lower voltage or higher clock at same voltage = lower VID
Maybe it can be found with wayback archievesThe Stilt on OCN like 8? years ago, explained it well.
Hm, could be interesting. BIOS support is questionable.Maybe missed,
i saw the cheap Pro lineup just recently as 5600 kits.
They definitely are capable, if they want.
EDIT:
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YesJEDECXMP 4800 C28-36-36 [Igorslab] & 5600 32-42-42 @ 1.2v
vs 5600 36-38-38 @ idk what voltage
Different ICs and smaller CAS/RCD delta.
EDIT2:
Its even worse
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4800 C41-41 @ 1.1v JEDEC.
Other was 1.2v XMP, not JEDEC.
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@tibcsi0407
Those were my Viper Hynix-M early on
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Hynix 6000 30-36 @ 1.3(5)v ~ (XMP 6000C36-36 @ 1.25v)
vs XMP
Micron 6000 36-38 @ 1.35v
If they are just 1-2 ticks worse, it sounds good
But i don't know. I was big amateur back then~
Were not new.
Current listed is not out yet.
Whatever 16gb pro OC lineup is supposed to be.
Other Pro lineup are brand new too
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Soo they do play with marketing a bit
JEDEC 5600 rating is 46-45 @ 1.1v .
They dont sell slower kits because ICs are 5600 rated not 4800. 5600 & 6000 kits only.
Then 36-38 is 1.35v rated. How they can call it JEDEC 36-38 is beyond me.
But with math, it still sounds ok actually. I'd like to try them. Whatever new they will release as 16gb option.
EDIT2:
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So its that @ 1.1v.
I guess they can do better as 5600 40-40 kits vs 46-45 @ 1.1v
But ya~
Curious
Hynix-A
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Definitely lower tier at low voltage.
Hi @Veii, how are you? I liked all your posts here! (I have a library of OCN bookmarks of your posts, many from AMD) I'm still working with the voltages, maybe you can help me with some advice since there are some points that I don't quite understand yet.Rules are dynamic .
Up to self-adjusting V/R - odt of sample .
Self-adjusting because up to leakage factor of sample.
High VID = leaky, Low VID = non-leaky.
Leaky = 1.48++
Non-leaky=1.38-1.42v
High SA , lower IVR VDDQ ⟺ Mem VDDQ Delta ~ because weak ODT
Low SA, big VDDQ Delta, because strong ODT.
VDD2 = ODT defined and sample leakage defined.
Rules adapt to CPU
VDDQ ⟺ VDDQ changes by capacity, board layout, board ODT/RTT tuning & Rodt state defined by sample and SA state.
When SA bug happens, depends on sample leakage factor.
Freeze on TM5 are ODT issues inside CPU. Not meme related
#0 are dropped links between CPU & MEM.
#6 is mem primaries or CPU IMC.
#8 CPU synchronization issue for writes. Writes are handled by the CPU.
Working order :
Know V/F Curve ~ to decide on VDD(2)_CPU
Decide whatever SA.
VDDQ training off.
Sample Max VDDQ⟺VDDQ delta and min delta till y-cruncher 90min+TM5 1usmus 25c.
Of both borders use 80-85% of median.
If 60 & 120 , use 90-105mV (steps 15mV).
If 75 & 150, use ~120-135mV
And so on.
Higher capacity, smaller delta.
2DPC, vs 1DPC ~ smaller delta.
Weaker board design ~ smaller delta.
Best “rules” I can give you.
Too much “it depends”.
InMem Delta rules :
Step 30mV.
60mV delta always works
105mV delta is a powering/rtt check
240mV delta about user max ~ seen functional but never on stock RTTs.
300mV delta is PMIC max.
VDDQ⟺VDDQ is crucial
Hi @tibcsi0407, how are you? I just realized I just realized that you are from Hungary, you know that my parents are from Hungary, in fact I am a Hungarian citizen but I was born in Argentina, and believe it or not, I still have not known the land of my parents. It's something I'm going to do this year!, Regarding the AC_LL, then if, for example, I define 0.6, do the values that I defined in the V/F that I shared with you in my previous post move to the right? I say, because one of the errors that I think I have is that P3 is very low from the factory, so I have to give it +35/40mv to keep it horizontal, but then to achieve the double S, I increase the voltage of P4 and P5 , and then eating with an undervolt for the rest of the curve, which I think is what causes CB23 to fail and everything in general. If so, maybe those values could work, but they are high jumps compared to my original curve, what do you think?The AC loadline moves every value up or down. So the graph moves parallel, shape remain the same, just with different values.
SVID behaviour is trained right now?
What's your current mem speed? Some of us experienced issues above 8400 with the new release.@tibcsi0407 so i swapped to the 1001 bios today and so far i just needed to change my offsets slightly otherwise memory worked fine with same settings from 0080 which is weird cuz 0904 for me was unstable in memory and cpu but 1001 is fine, but you also had a problem with this 1 lol stuff is so confusing i wish they would just flat out specifically list off the changes instead of some generic term " improved system performance " and im sure there is reasons they don't but damn is it annoying lol
Hi,Hi @Veii, how are you? I liked all your posts here! (I have a library of OCN bookmarks of your posts, many from AMD) I'm still working with the voltages, maybe you can help me with some advice since there are some points that I don't quite understand yet.
My mem kit is a Gskill 8000 2x16 A-Die at 1.45 XMP. (similar to the 7800 2x16 at 1.4v). Would my XMP value be the floor of VDDQ_mem? Or for example with a RON of 48/40-40-48, could VDDQ_mem go down?
I'm trying with the following values:
8200/8266 loose timings (38-49-49-49-65)
VDDQ_mem 1.45
VDD_mem 1.51 (following the 60mV rule)
VDDQCPU-TX+ 1.23v it seems that the lower the better (it would be an objective delta, right?)
MC 1.48v (I didn't understand when you said that Know V/F Curve ~ to decide on VDD(2)_CPU). How can the MC value be interpreted on the V/F?
SA 1.18, I notice that the lower it is, the faster YC VST-VT3 works. The higher the SA, the slower the execution of VST-VT3. considering the detail I have between VDDQ and TX.
Regarding my 14900k CPU, I understand that it is non-leaky, my V/F is on the edge, at 1423 maximum. I'm working on it with the help of
@tibcsi0407, he did an impressive work!! Thanks @tibcsi0407! 🙌
I didn't understand when you say "of both borders use 80-85% of median", If 60 & 120 , use 90-105mV (steps 15mV). If 75 & 150, use ~120-135mV. I don't understand what you mean by the "borders", it went directly to a target of max 230mv for the 16GB kits. Before, I left TX in Auto which gave me a fixed value of 1.35, just 100mV of delta. I'd like to understand this concept so I can build my funtation well. Thanks
Another point, I realized that a Pcore, 7, shoots up in temperature. It is always the same as in the transitions from VST to VT3 (mostly in VT3), having a current peak, it fails. Can a single core be limited with an offset? I know it's pretty basic, but I don't know if it's better to touch the entire V/F or add an offset to a Core. Before, this error did not appear because I always had a limit, either PL1/2 or an AVX -2/-4. and with that I was at 253/280. Now without limits, I can reach ~310W but I notice that all the processors have relatively good temperatures except one.
You taught me a while ago how to define RTTs, in fact before with my previous 13700k CPU, I always used them flat, the adapted version of Shamito, 40-34-34-34/240-0-0/60(80) - 40-40, now I'll leave you by car. And for 8200/8266, 172 / 90 in CTL0 DQVrefup/down. For now I only have the RONs and CTL0 DQVref set, RTTs in Auto. Is it okay for me to start leaving RTT on Auto for now?
Thank you very much as always!
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Hi @tibcsi0407, how are you? I just realized I just realized that you are from Hungary, you know that my parents are from Hungary, in fact I am a Hungarian citizen but I was born in Argentina, and believe it or not, I still have not known the land of my parents. It's something I'm going to do this year!, Regarding the AC_LL, then if, for example, I define 0.6, do the values that I defined in the V/F that I shared with you in my previous post move to the right? I say, because one of the errors that I think I have is that P3 is very low from the factory, so I have to give it +35/40mv to keep it horizontal, but then to achieve the double S, I increase the voltage of P4 and P5 , and then eating with an undervolt for the rest of the curve, which I think is what causes CB23 to fail and everything in general. If so, maybe those values could work, but they are high jumps compared to my original curve, what do you think?
Oh, my SVID Behavior is Trained, and my MCE set to Enable Remove All limits. If I set ASUS MultiCore Enhancement [Auto – Lets BIOS Optimize], it set PL1 to 253W. I don't understand why it doesn't do it to you, but every time I select that, PL1 option it goes to 253. Even if I disable the TVB Voltage optimizations like you have. The only way to not limit anything is by setting MCE to "Enable Remove all limits"
Thanks!
Looks cool.aybe you can raise the 51X point a little and you will get the shape. How is the performance?Hi @tibcsi0407,I just tried AC at 0.6 and the curve looked much better, I just corrected P3 so that it doesn't go down, and eating at 719 instead of 711, I think it looks much better, even without achieving the double S shape
It seems much better, doesn't it? Thanks
I see.I will try it later too to find out what did they change, but atm I had to come back to 0081. It works like charm.
Actually ME version is the same afaik, so it's not a problem to bounce back without BIOS switching. CPU Microcode is updated in new BIOS.
Maybe they are preparing for KS launch.
mmmmHi @Veii! I'm also so so, but still pushing. Long story short, there was once a very happy OCN member with a good setup for his 13700k and 7200 with a Hero . But well, the desire to improve components and performance made me change everything. I bought an Encore, I managed to reach 8266MT/s with false stability, since by mistake, like many of us, I limited the voltage, in my case with an AVX offset, that's why YC never failed. Then I bought some 8000 2x16 Gskill A-die memories, to lower the voltages and temperatures a little, and until then, everything was fine. Then I bought the 14900k, which to my surprise and because it was a first attemp of purchase on Amazon US, I got a good one, SP105.
I realized from the progress of @tibcsi0407 what had advanced and one of the things that surprised me and you mentioned to me in this last post, that my SA was very high, and I didn't understand why so many users used such a low SA with an Apex.
I have two childs, they played Fortnite or Roblox, every so often an error 41 would appear and it would crash or reboot.
I am not sure for how long this will remain the case with SA/IVR VDDQ.This configuration at 8000 was not stable, and I passed a little YC (maybe that's the error) and then TM5, then Karhu 9hs... and cold boot... I went to 8266 taking one of your recommendations from a previous post
What I did was, I lowered VDDQCPU to 1.22 and SA rised to 1.21 I realized that at 1.18 it failed quickly, perhaps TX at 1.22 is too low for VDDQ 1.45. I know SA can't get above TX, that's why they are so close.
IVR VDD/Q 1456-1220What I did was, I lowered VDDQCPU to 1.22 and SA rised to 1.21 I realized that at 1.18 it failed quickly,
MVDDQ is not the fixed variable.if VDDQ_Mem is a fixed variable, and the delta is between 180 and 230mV, it would be at the maximum of that delta, I could raise it, but there are three variables.
use the latest TM5What do you recommend me? I'm a little lost and frustrated...
Thanks like always!
Too extreme.
Die Berichte klingen nach einem überdruck Problem. Bzw eher ein krummer mountheatkiller, kein Frame. Alles normal. Eingespannt, Kühler mit Federschrauben, u-Scheiben. Hatte nie Probleme bei dem.
CPU Write error.mal was versucht.
tx 1.4
sa 1.20
imc: 1.38, zeigt immer 1.35 an
vdd 1.56
vddq 1.50
erro bei Test 8 nach 40 min.
Laut Tabelle error 8: to low WTRS, oder to high WTRL oder höheres WTRS stellen... was sollte man eher verstellen?
Abseits dem, ja55 kann leider fast jede Spannung verursachen. Genauso sind Timings möglich.
Man kann es meist ein wenig eingrenzen wenn man beobachtet wann der 55er kommt.
Also wie weit der bootablauf geht. Wenn er schon 2-3 neu ansetzen muss ist man eh weit von dauerhafter Stabilität entfernt.
Kommt der 55er direkt im ersten Versuch und im normalen trainings Verlauf dann sind es meist nur Spannungen.
Wieso möchtest du die Timings abseits dem XMP ändern, es läuft jahab Deine Werte übernommen, aber warum die Spannung ändern?
Yes, and my first name is Laszlo, but here Martin is more "common", and yes, the world is small!Hi,
Yes,I noticed first time your account name on OCN. The world is small. ☺️
I like the news shape better. Did you check the stability?
I believe MCE sets the option based on your cooling performance.
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Looks cool.aybe you can raise the 51X point a little and you will get the shape. How is the performance?
The only thing I don't understand is why one core, the P7, is rising in temperature compared to the rest, it is an important difference.
For me the top ratio, which is 62X on two cores works only like this. I tried negative offsets on top, but I got crashes in some apps. With a little + offet it works fine, but it's CPU and ratio dependent.Too extreme.
Most harsh loads are near 4.7-4.8GHz.
The ceiling needs to be rather curving downwards, else on TVB+ you spike too high
Slightly flatten higher, and pushed up with AC_LL doesnt want to work ?For me the top ratio, which is 62X on two cores works only like this. I tried negative offsets on top, but I got crashes in some apps. With a little + offet it works fine, but it's CPU and ratio dependent.
That VID is funnily only the P0 core, but I have Core 4 and 5 set to get highest ratio.I see you spike too high. till 1.55vid
This is a 14th gen feature.
A new throttle system , up to 105° per core or 95° whole CPU.
Fused Curve is rated till that target.
Ok, I'm going to do that, could I start with 8000, which is the XMP Profile? Something you told me is that VDDQ and TX are a fixed variable, my question is if I should take as an initial value, for example, 1.45V (which is the XMP value for 8000 2x16 A-die) for a 1.25v TX? , or do I look for a lower value, for example 1.4V (mem) / 1.2 (tx) as borders? That is my great doubt!use the latest TM5
Drop SA to 1.14v level and start with 7800MT/s.
Figure median of delta out. till TM5 gives a #0 or #6.
Keep VDD2 near 1.4v
I say because the Encore trains everything, badly, but it trains, I mean, it boots, and I have constant crashes in Windows (of course on a test partition), but all the BSOD Error 41 are for this, for trying to find the VDDQ Delta. Thanks for your help as always @Veii!!I guess play with VDDQ delta.
In 15mV steps till you fail boot. Then in 5mV steps up and down till it passes.
This could be due to the IHS. A delid / relid with TGC would help you a lot on your CPU temps.in my graph it is more noticeable how the peak of the PCores occurs at a maximum of 89 and the P7 shoots up to 97.