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Given you will also be required to run hours on hours harsh load.I don't want to help you any further degrading your CPU. Because it likely already will be happening.
Without removing this old method approach and making margins for memOC
You will either reach nothing, or if kept on old methods ~ permanently damage cpu
I don't want to support that, @Hemu2K soo please work on the first importance
VID leveling and V/F curve.
Samples are overvolted to make margins for memOC
But cores don't need to stay overvolted and take priority from rest of important parts on the cpu.
Fix cores first (ring scales automatic), before you proceed.
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Unfortunately no, hahaIs it possible to test only one of them at a time and leave the others on auto, or should I change all of them together?
Auto training = read user value, remain to lookup table, if non try to train
Disable training = enforce user value and if non , check lookup table. If non, fail boot
Enabled training = override lookup table, train new values which may or may not be good ~ up to cpu stability.
WR, NOM, PARK go together
PARK & PARK DQS go together
Sadly no~~
You can "just" change NOM & PARK together and leave WR be
But if WR changes, PARK and NOM scale will change. Their effectiveness too
Change on PARK & NOM go hand in hand with RRD & WTR.
Absolutely zero solo value exists anywhere in memory. Often its just a pair. Sometimes a tripple.
VID-SA, IVR VDD2, IVR VDDQ is a trio. NOM WR PARK is a trio. RFC XSR REFI + CPDED, CKE, XP both are trios.
RCD RTP are a duo, RC RP + VPP_MEM VDD_MEM are a duo. RAS CAS CWL are a trio.
WR WTRS/L are a trio. Aaand so on.
Its bad to only change one value and track for change. Side issue vs main issue.
🤭
But RTT testing is easy with TM5
First check current TM5 progress on 8600 before we create more rabbit holes.
Cycles you always want 25. 1usmus_v3 is not a normal discharge test like HCI/Karhu or anta's config.
EDIT:
RTT testing is even easier on super high voltage. Because DIMM-PCB will be unhappy with 1.6v or 1.7v.
DIMM Fingers charr around 1.8v constant or 1.95-2.1v spikes.
Mem doesn't die with 2.15v (idk about all, seen RDIMM catch flames, unclear if 2.2 or 2.5v bugs) and mem can complete 25cTM5 with 1.8v bugs.
Just require cleaning or soft goldfinger's sanding afterwards, due to oxidation.
RTT Testing <- Timings irrelevant, timing balance relevant.
RRD, WTR , RTP , WR balance relevant ~ everything else , irrelevant.
https://www.overclock.net/threads/o...memory-stability-thread.1628751/post-29081028 I cant find the original pictures right now
^ old OC-Mode highvoltage (hex translation) bugs
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