[Sammelthread] Intel DDR5 RAM OC Thread

[Veii]

Yes, should be okay, but pden 2 could mess the powerdown. Maybe it's not a good idea. It's a Buldzoid thing. 🙃

Its hard to believe this would be a recommendation
Maybe its just a reading mistake

RBL & WBL = 16
This is not a speed timing, this is a hardware design limitation.
DDR2 was RBL/WBL = 4

 

[tibcsi0407]

It's hard to believe this would be a recommendation
Maybe it's just a reading mistake

RBL & WBL = 16
This is not a speed timing, this is a hardware design limitation.
DDR2 which is RBL/WBL = 4
Anhang anzeigen 961818

Buildzoid use this in his YouTube videos. And many users just copy that.

 

[Veii]

Buildzoid use this in his YouTube videos. And many users just copy that.

I think its just something as simple as a "late night reading mistake".
RPDEN
RDPDEN
PRPDEN
all look nearly the same

 

[tibcsi0407]

I think its just a late night reading mistake.
The value difference is too big.

You can not run neither CAS nor CWL at 2.

I know it's hard to believe, but you can see it in most of his videos.

In the meantime I started to play with the RTT's. The combination you suggested got error code 55. Probably due to the low voltages.
I got a tip from @CarSalesman last year, so tried it. 34-120-80-40-40
I was able to boot it, but got error 0 iin 20. minutes. So I upped the Dqs to 48, now I got this:

Need more tuning, but could be a good base.

 

[Veii]

In te meantime I started to play with the RTT's. The combination you suggested got error code 55. Probably due to the low voltages.

80 WR is weaker

Then 80-80-60-40-48

 

[tibcsi0407]

80 WR is weaker

Then 80-80-60-40-48

Thank you. I will check if I can boot this with the current voltages. I am in the beginning of a long trip with this I believe.

 

[zebra_hun]

Guten Abend!

Die Profis redet über extreme OC, ich hole jetzt andere Ergebnisse
Ich habe eine ziemlich gute 13700k, heute eingebaut.
Ich denke, es schaut nicht so schlegt aus. Ja ok, nicht so kraftig wie 14900k, aber gehts.
Delided, IHS drauf, LM ist zwischen Chip und IHS.
WLP ist zwischen Block und CPU.
13700k ist allcore 53p 42e 45r, und 2 Kerne boosted 54x.
Ich habe die ganze CPU Einstellungen so gelassen, wie Default ist. Nur habe ich die Best Case Scenario benutzt, die ein sehr gute UV ist.
Alle andere sind Default. Es gibt kein noch V/F, und solche Dinge.
Vcore getested kurze SFT, wenn es passt, dann alles passt. (Erste Bild)
Es war mit 5600 JEDEC, und danach 8000MHz eingegeben.
25 Rund TM5 ist sofort gegangen, und nacher VST/VT3 habe gestarted.
Wow, es hat mich gewundert, 50 Mins is gelaufen.
Nochmal, noch kein OC gibt, alles ist Default, nun 8000 plus paar Werte eingegeben.
Temperaturen sind auch schön

Ich mache weiter dann, nie aufgeben

Schöne Nacht u. WE an Alle!
Prost, zeb

Beitrag automatisch zusammengeführt: 20.01.2024

Update:
Noch paar Werte eingegeben, und genau 50. Minutes Error. Immer VT3... grr, ich mag kein VT3 Test

 

[mahaudi]

Soviel wie ich weiss und was ich gesehen habe der erste Daily Screen auf einem Tachyon Z790 @ 8533 Mhz

Rams sind wassergekühlt mit einem Bykski RAM-Cooler

( Das war wirklich viel Zeit und Arbeit ).......werde das noch weiter verfestigen ....weil später kam leider noch ein Fehler bei ~ 1:20 Std.


PS: Ich hatte ja mal vor einer Zeit gefragt was es überhaupt bringt auf Wasserkühlung für die RAMs zu bauen .

Aus jetziger Erfahrung kann ich sagen das das enorm Stabilität bringt. Das hätte ich früher machen sollen . Das hätte mir viel Zeit ersparen können.

Eventuell kommt noc heine ICEMAN RAM Cooler ...um das Delta noch weiter zu senken.

Mit dem Bykski habe ich ein Delta von ca. 7-8°c zur Wassertemp

 

[tibcsi0407]

80 WR is weaker

Then 80-80-60-40-48

For RD I need low (strong) value to even boot it. (48 is the highest which can boot) Is that means I already have high voltage on my dimms?
Should I lower the Voltage and increase the RD to 80?
Current state on 34-80-60-40-48. It's still running. RX-DFE on auto atm.
I was looking for the detailed comment from you about RTT's, but can't find it. Should be bookmarked somewhere I believe.

Let's see if lowered Dqs fix it:

 

[tibcsi0407]

Hi @Veii

Some progress.
RTT is on auto, but changed SA to 1.23V and TX to 1.33V MC to 1.518V.
I believe I will play with TX and MC further.

 

[Veii]

Should I lower the Voltage and increase the RD to 80?

Dont touch voltages

If you get RTTs figured out without DFE override, it will be top

RTTs need to be able to run and cover 1.44-1.6v
Actually they should be fine till 1.65 even

Current state on 34-80-60-40-48. It's still running. RX-DFE on auto atm.
I was looking for the detailed comment from you about RTT's, but can't find it. Should be bookmarked somewhere I believe.

Let's see if lowered Dqs fix it:

DQS either one above or one bellow PARK
Dont match it.
Matching will require higher delta on pmic, to get some sort of usable distance between voltages.

NOM shenanigans indeed sounds like some different/odd behaving pcb.
I wonder.

Tuning RTTs on VDD/Q matched (in mem)
May be a good idea
But this will mess too much up.

Ya it looks fine.
You can play around if one NOM needs to be off or on
And you can play around between 40-48 PARK
If that changes how weak one NOM can reach.
Target remains 80-80. Those are not dual sided.

Beitrag automatisch zusammengeführt: 21.01.2024

Hi @Veii

Some progress.
RTT is on auto, but changed SA to 1.23V and TX to 1.33V MC to 1.518V.
I believe I will play with TX and MC further.

Sorry, today has been one of those away from home days.

We do want low SA tho.
Can you track how low you can go without y-cruncher loosing and/or rather gaining computational speed ?

Should be like 6* 10 min work at worst.
Move in steps of 5-10mV. Dont move over 10mv Steps

 

[tibcsi0407]

Don't touch voltages

If you get RTTs figured out without DFE override, it will be top

RTTs need to be able to run and cover 1.44-1.6v
Actually they should be fine till 1.65 even


DQS either one above or one bellow PARK
Don't match it.
Matching will require higher delta on pmic, to get some sort of usable distance between voltages.

NOM shenanigans indeed sounds like some different/odd behaving pcb.
I wonder.

Tuning RTTs on VDD/Q matched (in mem)
May be a good idea
But this will mess up too much.

Ya it looks fine.
You can play around if one NOM needs to be off or on
And you can play around between 40-48 PARK
If that changes how weak one NOM can reach.
Target remains 80-80. Those are not dual sided.

Thank you. I believe the top settings could be the foundation now I will do more with RTT's again.
I start to believe that it could be doable. 🙃
Should I touch the ODT too?

 

[Veii]

@zebra_hun
Ring hits ICCMAX.

No way around undervolt to lower UncoreVID.
Or limiting max ring multiplier.
Hitting PL4 means throttle.

How would it throttle.
At best package throttle, at worst voltage supply throttle

What happens if voltage is throttled too much ~ craaash 🤭
Mostly on cache

EDIT:
Unlimited ICCMAX makes no sense,
As you trade away cpu lifetime for "short time stability"
Fixing curve is the path~
To lower one part of supply, leave more margins till ICCMAX. Leave more margins for IMC.

Beitrag automatisch zusammengeführt: 21.01.2024

Thank you. I believe the top settings could be the foundation now I will do more with RTT's again.
I start to believe that it could be doable. 🙃
Should I touch the ODT too?

You can just reuse them.
SA, VDD(2)_CPU, VDDQ_CPU
It either runs or doesnt.

But i would focus to keep SA lower.
VDDQ <-> MEM is an own topic.
Dont mind it for now.

We both know that things are cross connected
Low SA baseline is important. Else other voltages spike up and some lower.
Generally target since recent bioses is strong ODT.

Need to work with it.
Increasing SA is not the path to take.

---

@mahaudi Karhu 20000%
Es braucht solange es braucht

 

[mahaudi]

Das ist doch ein schönes neues Daily-Setup

8400 CL 34 47 46 32 @ 1.590v

Richtig guter Memory Score @ Geekbench 3......und AIDA64 sieht auch gut aus.

 

[tibcsi0407]

@zebra_hun
Ring hits ICCMAX.

No way around undervolt to lower UncoreVID.
Or limiting max ring multiplier.
Hitting PL4 means throttle.

How would it throttle.
At best package throttle, at worst voltage supply throttle

What happens if voltage is throttled too much ~ craaash 🤭
Mostly on cache

EDIT:
Unlimited ICCMAX makes no sense,
As you trade away cpu lifetime for "short time stability"
Fixing curve is the path~
To lower one part of supply, leave more margins till ICCMAX. Leave more margins for IMC.

Beitrag automatisch zusammengeführt: 21.01.2024

You can just reuse them.
SA, VDD(2)_CPU, VDDQ_CPU
It either runs or doesnt.

But i would focus to keep SA lower.
VDDQ <-> MEM is an own topic.
Dont mind it for now.

We both know that things are cross connected
Low SA baseline is important. Else other voltages spike up and some lower.
Generally target since recent bioses is strong ODT.

Need to work with it.
Increasing SA is not the path to take.

---

@mahaudi Karhu 20000%
Es braucht solange es braucht

I will try to reduce it. Tomorrow will check the current setup with lower SA.

 

[Veii]

I will try to reduce it. Tomorrow will check the current setup with lower SA.

If it fails like every 4 cycles , that should be no work for you

 

[robonz]

Das ist doch ein schönes neues Daily-Setup

8400 CL 34 47 46 32 @ 1.590v

Richtig guter Memory Score @ Geekbench 3......und AIDA64 sieht auch gut aus.

Mit 8400C34 kannst du auch bessere Effi erzeugen ; 8400C36 mit nur P55/R50



Ein bisschen mehr geht auch noch 😇

 

[tibcsi0407]

If it fails like every 4 cycles , that should be no work for you

We will see. 🙃 I think it will be okay, but will see that.

 

[epilef]

Registered in this forum to try my luck finding tips.
Im currently on Encore with 7800Gskill Adies
I believe in "goal is always to overshoot in defensive side of things instead of always being at 1.0 ratio of cooling/clocks"

Im with barrow aluminium heatsinks with holes on top (great btw, 1.5mm pads) + noctua fan 2000rpm at ram

I did overclock to 8000c36 and 7800c34 but i didnt really gained anything in games and honestly i just want to gain MORE stability
I tried read about skew odts but honestly i am too dumb and dont have an osciloscope to really see it and hate doing guesses.

Im using xmp tweaked with few changes and zero voltage changes, maybe shamino settings is better than guessers in OCN and my guesses.

if anyone has an skew/odt recommendation to make what i have even more stable, thats my goal
any gain that isnt really pushing speeds
even lower vdd/vddq ram i accept any tip

even if no answers , the forum looks great, had alot of good reads.
im from brazil i use translate
edit: this is retrain stable 24h karhu 1h vst/n63/vt3 and performance is good, just wanna see if i can try anything else

i used to read recomendations from pahktunov/vei
but in ddr5 im just lost when it comes to ram powersaving(ppd and etc) and other uncommon settings, and encore have literally all, its depressing not know

 

[Veii]

the forum looks great, had alot of good reads.

success 🤭

If you read all past 10-15 pages
I dont know what to add ~ all is written

Im using xmp tweaked with few changes and zero voltage changes, maybe shamino settings is better than guessers in OCN and my guesses.

if anyone has an skew/odt recommendation to make what i have even more stable, thats my goal
any gain that isnt really pushing speeds
even lower vdd/vddq ram i accept any tip

it just doesnt work that way
Being served on gold spoon - works for one person, doesnt work for other

And you dont learn by reading
But by trying out what you read.

No memory related voltages on auto
no cpu fixed clock, no cpu fixed voltage

I'm sorry if this comes over rude
But question read like , "explain me everything"
Ask question by question, and maybe it can be answered

Every question maybe has long or short explanation.
Its too much work and discouraging when asking "explain me everything".

ODT and RTT depend on mainboard
Depend on dimm
Depend on used voltage ~ which depend on CPU sample
Depend on PLL state.
Depend on hidden Bios settings, changing every 1-2 Bios releases.

I dont know how to explain or answer this.

 

[epilef]

I'm sorry if this comes over rude
But question read like , "explain me everything"

Its very fine.
I dont know what to ask

Thing is i dont know what I am looking for. if there is something to look for

In past i would disable powerdown and selfrefresh, reading a bit aparently disabling it dont even disable it fully (and lowering the timings make pyprime faster so it does something)

and even if i set odts that work, how im supposed to know if my signal is less noisy/more correct

depth of knowledge = money and i dont have 100k$ for osciloscope xd

so maybe hints from ppl that know ppl with it. idk

being able to SEE is the first step to getting results, I honestly dont know how im supposed to know if X or Y is working just by stressing. it seens very guessable

edit: ram/latency is king of optimization so im just trying to make mine better while not pushing any stability boundaries

 

[Veii]

and even if i set odts that work, how im supposed to know if my signal is less noisy/more correct

By pushing boundries and seeing what sticks
One can need lower voltage but still limit in max clock = too noisy
One can need much more voltage, but allow to scale higher than the dimm pcb was designed (example DDR4 , weak A0 PCB)
If you either push much, or start to learn on what many people call "g*rbage tier" or just bad bad cheap gear
You will understand when something "scales well".

reading a bit aparently disabling it dont even disable it fully (and lowering the timings make pyprime faster so it does something)

This is the fun thing i had to learn
Lower is always faster somewhere.
On some application with some dataset size, big or small
You will always find some application where you can say "see it scales"

But thats always the case.
Lower is in specific type of read combinations or read, no-operation, read ~ always faster
some dont even leave one IC.

The question then becomes not about if the timing scales, but what was the tradeoff
What did you influence before set timing an what follows after set timings
Maybe its complicated and sounds like nonsense for somebody who only focuses on the result
But thats how i learned to stop just pushing pushing. And try to learn what happens and what do i pay with my changes

No timing goes alone
Absolutely zero.
Minimum has two links , often its 3 (before, target, effect after)

depth of knowledge = money and i dont have 100k$ for osciloscope xd

Money or lifetime , or connections
If you dig enough even if nobody wants to help you (take me as the best "worst example")
you still learn. Maybe not in 1month, maybe its difficult for 5 months
But after 6-8 years being silly and fooling around ~ you sloowly start to understand.

I'm still novice, but even if you hold bad of me (example)
I learned a bit. Day by day more. Soo if low-iq me can do it ~ everybody can.
just work harder 🤭 and don't forget your goals

edit: ram/latency is king of optimization so im just trying to make mine better while not pushing any stability boundaries

This might sound naive from me
But it is really not the case

Latency matters only to be faster than inter-thread/inner-cpu latency
Soo priority to leave cache and leak to mem, vs other cores ~ is higher.
If memory access is fast enough, decision to pick that path is rather whats going to happen ~ vs make roundtrip and stay on cpu side.

Latency only is a variable vs how the cpu behaves.
Some SKUs scale more, some less, some who use huge L3 cache or fast V-Cache
~ its hard on them to tell to leak to memory, when memory maybe differs between 15-20GB/s, but internally it runs at 500GB/s with same latency . . . for example
^ like why should CPU even bother to leak to mem, instead of wait a bit and process it much faster or split around other free cores~

Many many IF's
Try to get familiar with SiSoftware Sandra.
Don't rely too much on those little memory filling random-type of benchmarks.
They will show one scenario, but memory can be optimized, for all sorts of different workloads.
Its not a simple or straightforward thing.

Beitrag automatisch zusammengeführt: 21.01.2024

Latency matters only to be faster than inter-thread/inner-cpu latency

Because how would you define "faster" or "slower"
if you only test in one made up coded scenario.

How can you tell its actually "faster".
How can you tell its not just using one timing more, because the target/workload is just such little one.
Try to look at the bigger picture~

No timing goes alone
Lower Clock = lower visual timings.
but timings are just placeholders. The value is just visual without any meaning
It gets a meaning when you compare it to what type of clock ~ how much, it actually is
And still then - first target is stability high clock.

Timings are just gifts. Extras. They have low priority.
How things interact with each other, is more important.
And of-course absolute stability.

 

[epilef]

im really demotivated to deep dive cause it will be guesses..

an pc is faster cause he can do instructions faster
not cause it has been overclocked higher "grain of salt"xd
im more interested in architecture and his awful relationship with scheduler/os

but i came to the right place, the insight fullfilled me on what to do a bit
most overclocks i see put more stress on the arch and is just average fps streetching with barely any gains on lows where it actually improve ur experience

i cannot get access to any good pdf to read (last time i tried some intel pdf i got the text "it's a confidential slidedeck so I'm not too comfortable putting it "out there" without the proper approvals") but still managed to find a bios setting that learn that it was Power Control Unit/throttling that i was able to disable and get 80w more of my cpu at same load, was fun)
and too dumb to get an conclusion from jedec


just one objective question, do you think i am wrong of disabling powerdown and set timings to minimum register
it showed no signs of unstability, improved some benchs(will try what u recommended), and i do that cause of 10y old pdfs that i read about them,

 

[mahaudi]

@ robonz ...geilstes 2 DIMM Board " EVGA DarK "

Echt schade das EVGA nicht mehr weiter macht in dem Bereich.

 

[Veii]

just one objective question, do you think i am wrong of disabling powerdown and set timings to minimum register

YES !
Because powerdown "usage" changed

Now powerdown is part of self-refresh
and self refresh is part of FGR. Clock-Halting is also a fun new thing.

FGR especially is mostly used on LPDDR4 (onwards) and you will find information on GDDR5++
Everything LPDDR4 can do, DDR5 can do.
Just DDR5 changed from where many things were under MSR ~ they are now API calls.

DDR5 became a standalone ecosystem similar to your GPU.

---

Setting timings to lowest point, will harm some timings before and some timings after.
// Because many things - multiple timings happen at the same time !

JEDEC paper i still "don't understand" fully.
But they (memory committee, jedec is there for all sorts behavior) - pads/paste/nand-flash/thermal behavior, pcb layering and targets . . . many things
Are the first source you can use as "this is how it will be , if nothing was changed mid or past design" . Especially when DDR5 is still in its young age.
Like "this is the target and this is how it has to be. Change it up a bit , but still this is how it behaves and can behave". The bare minimum required targets for IC design.

On that part you can be sure.
Its like other global comitee's that set the standard and thats how things are and will be.
Its your book to see if you misunderstood something and check if you broke some rule.
Memory will do its best to correct and jedec papers do not define all sort of use-cases

For this you have to explore private researchers

Spoiler

Request Rejected

Request Rejected

Request Rejected

Request Rejected

https://tuprints.ulb.tu-darmstadt.de/12975/1/2020-07-28_Angeli_Nico.pdf

^ couple interesting ones ~ last is complex and becomes interesting on AMDs side.

For example , and similar from https://ieeexplore.ieee.org/
Be it for GDDR or LPDDR or own designed FPGA circuits.
I can guarantee there is always some snippets of information that you can use

If you search how to get those papers, it will help.
I can not be the person that helps in going around university restrictions.
Even if as researcher person think knowledge should be free for everyone.

Nvidia has early on employed some tallented Memory Researchers
There might be some information out on this for LPDDR4 and GDDR.
There are parallels. Just the link layout and location layout differs a bit.
Else they are still very similar to consumer ICs.

EDIT:
Another location you can dig is with Baidu search (chinese) *
For example on forums like https://blog.csdn.net/
Or the korean field on forums like https://blog.naver.com/

Its unfortunate that NDA mentality is a thing.
Rivalism and secret-keeping is strong in this industry Unfortunately that halts global progress, but money i guess~

* Soo you still need to work a bit for your goal.
Just don't forget your goals ~ and if you learn or be successful, give back and help more people
If you don't, you do no change to this "hard to find information" issue. So other people will equally struggle like you did.

EDIT2:
Here are some writeups from one blogger on CSDN [CN]

Spoiler

DDR5时代信号完整性仿真帮你应对新的设计挑战_ddr5仿真-CSDN博客

文章浏览阅读3.9k次，点赞4次，收藏58次。2020年2月6日，美光科技宣布交付全球首款量产的低功耗DDR5 DRAM 芯片，随后，三星S20系列和小米10系列手机先后发布，全新的LPDDR5内存成为两家的共同卖点之一，这也预示着DDR5的时代即将到来。今天我们就来聊一聊DDR5的发展过程，设计难题以及如何通过仿真来应对DDR5设计挑战。本文主要目录：01.DDR技术的发展历程02.DDR5的出现，带来了哪些设计挑战？03.如何通过仿真及建模中的创新克服DDR5技术挑战04.DDR5仿真解决方案05.DDR5仿真实例..._ddr5仿真

blog.csdn.net

最新的DDR5标准简介以及规范协议验证介绍_ddr5构成-CSDN博客

文章浏览阅读5.5k次，点赞6次，收藏59次。内存(DRAM)作为当代数字系统最主要的核心部件之一，从各种终端设备到核心层数据处理和存储设备，从各种消费类电子设备到社会各行业专用设备，是各种级别的CPU进行数据处理运算和缓存的不可或缺的周转“仓库”，一个强大的核心处理单元也必须配备一个高速运转的宽通路的数据访问和存储单元。近20多年来，DRAM也快速地从20世纪末期的SDRAM发展到21世纪DDRRAM。在21世纪的前10年，DDR标准主要是个人信息处理终端的代表设备----PC和个人工作站类驱动，快速从DDR1演进到DDR3。而近10年来，进入移动互_ddr5构成

blog.csdn.net

DDR4 设计概述以及分析仿真案例_ddr需要驱动器和颗粒的ibis模型-CSDN博客

文章浏览阅读3.2k次，点赞3次，收藏36次。1.1DDR4与DDR3 不同之处相对于DDR3, DDR4首先在外表上就有一些变化，比如DDR4将内存下部设计为中间稍微突出，边缘变矮的形状，在中央的高点和两端的低点以平滑曲线过渡，这样的设计可以保证金手指和内存插槽有足够的接触面从而确保内存稳定，另外，DDR4内存的金手指设计也有明显变化，金手指中间的防呆缺口也比DDR3更加靠近中央。当然，DDR4最重要的使命还是提高频率和带宽，总体来说，DDR4具有更高的性能，更好的稳定性和更低的功耗，那么从SI的角度出发，主要有下面几点, 下面章节对主..._ddr需要驱动器和颗粒的ibis模型

blog.csdn.net

Memory Training、Testing and Margining-CSDN博客

文章浏览阅读2.8k次，点赞3次，收藏11次。DDR 内存训练/初始化期间会发生什么，它与制造测试或系统边缘验证所需的内容有何不同？在 Intel 平台上，BIOS 内存参考代码 (MRC) 用于初始化内存控制器并优化读/写时序和电压以获得最佳性能。MRC 非常复杂：它的工作是优化以 2GT/s 及更高速度运行的多条并行总线，并使它们充当“一个系统”。它通过使用复杂的方法来实现这一点，包括片上端接 (ODT)、读/写调平（使用“飞越”拓扑故意引入飞行时间偏差，从而避免同时发生的开关噪声）、Vref 调谐、CMD/CTL /ADDR 计时训练等方_memory training

blog.csdn.net

If you want to figure things out ~ you'll figure things out 🤭
But i've given enough, now its on you to dig and slowly with multiple readings try to understand

im really demotivated to deep dive cause it will be guesses..

And not only read and try to understand
But play around.
With imagining to guess, nothing works. With trial and error you will understand
Many people hand out information, but spoonfeeding is not ok.
"gifted" vendor-documents and knowledge are earned, not handed out just like this.

 

[K4PEMODE]

Yoo,

Moved to Z790 from AM5 and this are bit different here.

VST+VT3, TM5 and karhu stable base. I've made some very basic changes what did work with AM5.

Voltages are not minimized to lowest possible.

Any points for extra tightening?

 

[Veii]

VST+VT3, TM5 and karhu stable base

Yes ?
Where are they ?
Welcome 👋

 

[K4PEMODE]

Yes ?
Where are they ?
Welcome 👋

There is picture attachment, you cannot see it?

Here it is again

 

[Veii]

There is picture attachment, you cannot see it?

Sorry, I ment the quoted things.
In forums, its not common to work on "trust me" bases.
Looking for TM5 & y-cruncher screenshots.

Are they uploading still ?

 

[K4PEMODE]

I ask about the quoted.
In forums, its not common to work on "trust me" bases.
Looking for TM5 "stable" , y-cruncher "stable" screenshots.

Is it uploading still ?

Ah I see you want those screenshots, I do some runs for you.